DS2176 Datasheet, PDF (1/15 Pages) Dallas Semiconductor – T1 Receive Buffer

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FEATURES
§ Synchronizes loop–timed and system–timed
T1 data streams
§ Two–frame buffer depth; slips occur on frame
boundaries
§ Output indicates when slip occurs
§ Buffer may be recentered externally
§ Ideal for 1.544 to 2.048 MHz rate conversion
§ Interfaces to parallel or serial backplanes
§ Extracts and buffers robbed–bit signaling
§ Inhibits signaling updates during alarm or slip
conditions
§ Integration feature “debounces” signaling
§ Slip–compensated output indicates when
signaling updates occur
§ Compatible with DS2180A T1 Transceiver
§ Surface mount package available, designated
DS2176Q
§ Industrial temperature range of –40°C to
+85°C available, designated DS2176N
DS2176
T1 Receive Buffer
PIN ASSIGNMENT
SIGH 1
RMSYN ₂
RCLK 3
RSER 4
A5
B6
C7
D8
SCHCLK 9
SM0 10
SM1 11
VSS 12
24 VDD
23 SCKLSEL
22 SYCLK
21 SSER
20 ^SLIP
19 SBIT8
18 SMSYNC
17 SIGFRZ
16 SFSYNC
15 ALN
14 ^FMS
13 _S/P
24-PIN 300 MIL DIP
A ^{4 3 2 1 28 27 26}
5
25
B⁶
24
NC 7
23
NC ⁸
22
C⁹
21
D ¹⁰
20
SCHCLK ¹¹
19
12 13 14 15 16 17 18
SSER
SLIP
SBIT8
NC
NC
SMSYNC
SIGFRZ
28-PIN PLCC
DESCRIPTION
The DS2176 is a low–power CMOS device specifically designed for synchronizing receive side loop–
timed T–carrier data streams with system side timing. The device has several flexible operating modes
which simplify interfacing incoming data to parallel and serial TDM backplanes. The device extracts,
buffers and integrates ABCD signaling; signaling updates are prohibited during alarm or slip conditions.
The buffer replaces extensive hardware in existing applications with one “skinny” 24–lead package.
Application areas include digital trunks, drop and insert equipment, transcoders, digital cross–connects
(DACS), private network equipment and PABX–to–computer interfaces such as DMI and CPI.
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