MTP9006E3 Datasheet, PDF (1/6 Pages) Cystech Electonics Corp. – P-Channel Logic Level Enhancement Mode Power MOSFET

CYStech Electronics Corp.
Spec. No. : C733E3
Issued Date : 2010.07.09
Revised Date :
Page No. : 1/6
P-Channel Logic Level Enhancement Mode Power MOSFET
MTP9006E3
BVDSS
-60V
ID
-10A
Features
• Low Gate Charge
• Simple Drive Requirement
• Pb-free lead plating package
RDSON(MAX)
95mΩ
Equivalent Circuit
MTP9006E3
Outline
TO-220
G：Gate D：Drain
S：Source
G DS
Absolute Maximum Ratings (TC=25°C, unless otherwise noted)
Parameter
Symbol
Drain-Source Voltage
VDS
Gate-Source Voltage
VGS
Continuous Drain Current @ TC=25°C
ID
Continuous Drain Current @ TC=100°C
ID
Pulsed Drain Current *1
IDM
Avalanche Current
IAS
Avalanche Energy @ L=0.1mH, ID=-10A, RG=25Ω
EAS
Repetitive Avalanche Energy @ L=0.05mH *2
EAR
Total Power Dissipation @TC=25℃
Total Power Dissipation @TC=100℃
Pd
Operating Junction and Storage Temperature Range
Note : *1. Pulse width limited by maximum junction temperature
*2. Duty cycle ≤ 1%
Tj, Tstg
MTB9006E3
Limits
Unit
-60
±20
V
-10
-7
A
-40
-10
5
mJ
2
50
W
25
-55~+175
°C
CYStek Product Specification