MTP4060J3 Datasheet, PDF (1/8 Pages) Cystech Electonics Corp. – P-Channel Logic Level Enhancement Mode Power MOSFET

CYStech Electronics Corp.
Spec. No. : C563J3
Issued Date : 2012.01.16
Revised Date : 2012.10.11
Page No. : 1/8
P-Channel Logic Level Enhancement Mode Power MOSFET
MTP4060J3
BVDSS
-100V
ID
-27A
RDSON@VGS=-10V, ID=-20A 36mΩ(typ.)
Features
• Low Gate Charge
• Simple Drive Requirement
• Pb-free lead plating & Halogen-free package
RDSON@VGS=-4.5V, ID=-18A 41mΩ(typ.)
Equivalent Circuit
MTP4060J3
Outline
TO-252(DPAK)
G：Gate D：Drain
S：Source
G DS
Absolute Maximum Ratings (TC=25°C, unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current @ TC=25°C
Continuous Drain Current @ TC=100°C
Pulsed Drain Current *1
Avalanche Current
Avalanche Energy @ L=0.1mH, ID=-20A, RG=25Ω
Total Power Dissipation @TC=25℃
Total Power Dissipation @TC=100℃
Operating Junction and Storage Temperature Range
Symbol
VDS
VGS
ID
ID
IDM
IAS
EAS
Pd
Tj, Tstg
Note : *1. Pulse width limited by maximum junction temperature
*2. Duty cycle ≤ 1%
MTP4060J3
Limits
Unit
-100
±20
V
-27
-19
A
-108
-20
20
mJ
60
W
30
-55~+175
°C
CYStek Product Specification