MTF50P02J3 Datasheet, PDF (1/7 Pages) Cystech Electonics Corp. – P-Channel Logic Level Enhancement Mode Power MOSFET

CYStech Electronics Corp.
Spec. No. : C784J3
Issued Date : 2011.04.06
Revised Date :
Page No. : 1/7
P-Channel Logic Level Enhancement Mode Power MOSFET
MTF50P02J3
BVDSS
-20V
ID
-10A
RDSON(MAX)
58mΩ
Features
• Low Gate Charge
• Simple Drive Requirement
• RoHS compliant & Halogen-free package
Equivalent Circuit
MTF50P02J3
Outline
TO-252
G：Gate D：Drain
S：Source
GDS
Absolute Maximum Ratings (TC=25°C, unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current @ TC=25°C
Continuous Drain Current @ TC=100°C
Pulsed Drain Current *1
Total Power Dissipation @TC=25℃
Total Power Dissipation @TC=100℃
Operating Junction and Storage Temperature Range
Note : *1. Pulse width limited by maximum junction temperature
Symbol
Limits
Unit
VDS
-20
VGS
±12
V
-10
ID
-6.5
A
IDM
-40
Pd
30
W
10
Tj, Tstg -55~+175
°C
MTF50P02J3
CYStek Product Specification