MTB12P04J3 Datasheet, PDF (1/7 Pages) Cystech Electonics Corp. – P-Channel Logic Level Enhancement Mode Power MOSFET

CYStech Electronics Corp.
Spec. No. : C734J3
Issued Date : 2009.07.09
Revised Date :
Page No. : 1/7
P-Channel Logic Level Enhancement Mode Power MOSFET
MTB12P04J3
BVDSS
-40V
ID
-25A
RDSON(MAX)
12.6mΩ
Features
• Low Gate Charge
• Simple Drive Requirement
• Pb-free lead plating & Halogen-free package
Equivalent Circuit
MTB12P04J3
Outline
TO-252
G：Gate D：Drain
S：Source
GDS
Absolute Maximum Ratings (TC=25°C, unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current @ TC=25°C
Continuous Drain Current @ TC=100°C
Pulsed Drain Current *1
Avalanche Current
Avalanche Energy @ L=0.1mH, ID=-25A, RG=25Ω
Repetitive Avalanche Energy @ L=0.05mH *2
Total Power Dissipation @TC=25℃
Total Power Dissipation @TC=100℃
Operating Junction and Storage Temperature Range
Note : *1. Pulse width limited by maximum junction temperature
*2. Duty cycle ≤ 1%
Symbol
VDS
VGS
ID
ID
IDM
IAS
EAS
EAR
Pd
Tj, Tstg
MTB12P04J3
Limits
Unit
-40
±20
V
-25
-18
A
-100
-25
31.25
mJ
15
50
W
17
-55~+175
°C
CYStek Product Specification