S6J327C Datasheet, PDF (94/179 Pages) Cypress Semiconductor – 32-bit Microcontroller Traveo Family

S6J3200 Series
Symbol
FCLK_CD1B0
FCLK_CD1B1
FCLK_CD2
FCLK_CD2A0
FCLK_CD2A1
FCLK_CD2B0
FCLK_CD2B1
FCLK_CD3
FCLK_CD3A0
FCLK_CD3A1
FCLK_CD3B0
FCLK_CD3B1
FCLK_CD4
FCLK_CD4A0
FCLK_CD4A1
FCLK_CD4B0
FCLK_CD4B1
FCLK_CD5
FCLK_CD5A0
FCLK_CD5A1
FCLK_CD5B0
FCLK_CD5B1
FCLK_HSSPI
FCLK_SYSC0H
FCLK_COMH
FCLK_RAM0H
FCLK_RAM1H
FCLK_SYSC0P
FCLK_COMP
FCLK_CAN
Max *1
100
100
400
400
400
400
400
200
200
200
200
200
200
200
200
200
200
240
120
120
60
60
200
60
60
60
60
60
60
40
Max Value Combination
Function digit
3,4,5,6,7,8
Max *2
Max *3
100
100
100
100
400
400
400
400
400
400
400
400
400
400
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
200
240
240
120
120
120
120
60
60
60
60
200
200
66.7
80
66.7
80
66.7
80
66.7
80
66.7
80
66.7
80
40
40
Function digit
A,B,C,D
Max *4
100
100
320
320
320
320
320
160
160
160
160
160
200
200
200
200
200
240
120
120
60
60
200
80
80
80
80
80
80
40
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Remarks
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Notes:
− *1: Maximum clock frequencies when CPU clock = 240MHz.
− 232MHz or less is available for SSCG Down Spread on/off.
− 240MHz or less is available for PLL.
− *2: Maximum clock frequencies when CPU clock = 200MHz.
− *3: Maximum clock frequencies when CPU clock = 160MHz. This is also a combination of maximum clock frequencies for TC
FLASH Programming or Erasing.
− From *1 to *3, they are applied to the product series with function digit 3, 4, 5, 6, 7, and 8.
− *4: Maximum clock frequencies when CPU clock = 160MHz for the product series with the function digit A, B, C, and D. This is
also a combination of maximum clock frequencies for TC FLASH Programming or Erasing.
− Even if a combination of clock frequency is able to be configured by software, the frequency should be configured under
maximum frequency described in Table 8-1. For example, 80MHz of CLK_LCP0A seems to be configurable from both divided
240MHz and 160MHz of CLK_CPU. But each duty ratio of configured 80MHz as an internal signal is different from one another.
In this series, the 80MHz from the 160MHz divided by 2 can only be assured, but the 240MHz divided by 3 cannot be assured
from the internal timing design point of view.
− FCLK_TRC/2 (half frequency of FCLK_TRC) comes out of the trace clock port of package external pin.
− The frequency described in () is maximum output frequency of SSCG PLL / PLL multiplier circuit.
− The configurable minimum frequency of PLLn and SSCGn output is 400MHz.
− "Unused" means a clock source which doesn’t have any supply destinations. Configure it as disable with performing at the
lower clock frequency than the described maximum.
Document Number: 002-05682 Rev.*A
Page 94 of 179