STK22C48 Datasheet, PDF (9/14 Pages) List of Unclassifed Manufacturers – 2K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM

STK22C48
SRAM Write Cycle
Parameter
Cypress
Parameter
Alt
t_WC
t_AVAV
t_PWE
t_WLWH, t_WLEH
t_SCE
t_ELWH, t_ELEH
t_SD
t_DVWH, t_DVEH
t_HD
t_WHDX, t_EHDX
t_AW
t_AVWH, t_AVEH
t_SA
t_AVWL, t_AVEL
t_HA
t_HZWE ^[8,9]
t_LZWE ^[8]
t_WHAX, t_EHAX
t_WLQZ
t_WHQX
Switching Waveforms
ADDRESS
CE
WE
Description
Write Cycle Time
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
25 ns
Min Max
25
20
20
10
0
20
0
0
10
5
45 ns
Unit
Min Max
45
ns
30
ns
30
ns
15
ns
0
ns
30
ns
0
ns
0
ns
14
ns
5
ns
Figure 9. SRAM Write Cycle 1: WE Controlled ^{[10, 11]}
tWC
tSCE
tHA
tAW
tSA
tPWE
DATA IN
DATA OUT
ADDRESS
PREVIOUS DATA
tHZWE
tSD
DATA VALID
HIGH IMPEDANCE
tHD
tLZWE
Figure 10. SRAM Write Cycle 2: CE Controlled ^{[10, 11]}
tWC
t_SA
tSCE
tHA
CE
WE
DATA IN
tAW
tPWE
tSD
tHD
DATA VALID
DATA OUT
HIGH IMPEDANCE
Notes
9. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
10. HSB must be high during SRAM Write cycles.
11. CE or WE must be greater than V_IH during address transitions.
Document Number: 001-51000 Rev. **
Page 9 of 14
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