CY8C27466 Datasheet, PDF (9/39 Pages) Cypress Semiconductor – PSoC™ Mixed Signal Array

CY8C27x66 Preliminary Data Sheet
1.1.2 44-Pin Part Pinout
Table 1-2. 44-Pin Part Pinout (TQFP)
Pin
Type
Pin
No. _{Digital Analog} Name
Description
1
IO
P2[5]
2
IO
I P2[3] Direct switched capacitor block input.
3
IO
I P2[1] Direct switched capacitor block input.
4
IO
P4[7]
5
IO
P4[5]
6
IO
P4[3]
7
IO
P4[1]
8
Power
SMP Switch Mode Pump (SMP) connection to
external components required.
9
IO
P3[7]
10
IO
P3[5]
11
IO
P3[3]
12
IO
P3[1]
13
IO
P1[7] I2C Serial Clock (SCL)
14
IO
P1[5] I2C Serial Data (SDA)
15
IO
P1[3]
16
IO
P1[1] Crystal (XTALin), I2C Serial Clock (SCL)
17
Power
Vss
Ground connection.
18
IO
P1[0] Crystal (XTALout), I2C Serial Data (SDA)
19
IO
P1[2]
20
IO
P1[4] Optional External Clock Input (EXTCLK)
21
IO
P1[6]
22
IO
P3[0]
23
IO
P3[2]
24
IO
P3[4]
25
IO
P3[6]
26
Input
XRES Active high pin reset with internal pull down.
27
IO
P4[0]
28
IO
P4[2]
1. Pin Information
CY8C27566 44-Pin PSoC Device
P2[5] 1
AI, P2[3] 2
AI, P2[1] 3
P4[7] 4
P4[5] 5
P4[3] 6
P4[1] 7
SMP 8
P3[7] 9
P3[5] 10
P3[3] 11
TQFP
33 P2[4], External AGND
32 P2[2], AI
31 P2[0], AI
30 P4[6]
29 P4[4]
28 P4[2]
27 P4[0]
26 XRES
25 P3[6]
24 P3[4]
23 P3[2]
29
IO
P4[4]
30
IO
31
IO
P4[6]
I P2[0] Direct switched capacitor block input.
32
IO
33
IO
I P2[2] Direct switched capacitor block input.
P2[4] External Analog Ground (AGND)
34
IO
35
IO
P2[6] External Voltage Reference (VREF)
I P0[0] Analog column mux input.
36
IO
37
IO
IO P0[2] Analog column mux input and column output.
IO P0[4] Analog column mux input and column output.
38
IO
I P0[6] Analog column mux input.
39
Power
Vdd
Supply voltage.
40
IO
I P0[7] Analog column mux input.
41
IO
IO P0[5] Analog column mux input and column output.
42
IO
IO P0[3] Analog column mux input and column output.
43
IO
44
IO
I P0[1] Analog column mux input.
P2[7]
LEGEND: A = Analog, I = Input, and O = Output.
June 1, 2004
Document No. 38-12019 Rev. *B
9