CY7C64713 Datasheet, PDF (9/55 Pages) Cypress Semiconductor – EZ-USB FX1 USB Microcontroller Full Speed USB Peripheral Controller

CY7C64713
Endpoint RAM
Size
■ 3 × 64 bytes (Endpoints 0 and 1)
■ 8 × 512 bytes (Endpoints 2, 4, 6, 8)
Organization
■ EP0—Bidirectional endpoint zero, 64 byte buffer
■ EP1IN, EP1OUT—64 byte buffers, bulk or interrupt
■ EP2, 4, 6, 8—Eight 512-byte buffers, bulk, interrupt, or
isochronous, of which only the transfer size is available.
EP4 and EP8 are double buffered, while EP2 and 6 are either
double, triple, or quad buffered. Regardless of the physical size
of the buffer, each endpoint buffer accommodates only one full
speed packet. For bulk endpoints, the maximum number of
bytes it can accommodate is 64, even though the physical
buffer size is 512 or 1024. For an ISOCHRONOUS endpoint
the maximum number of bytes it can accommodate is 1023.
For endpoint configuration options, see Figure 6.
Setup Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup
data from a CONTROL transfer.
Default Alternate Settings
In the following table, ‘0’ means “not implemented”, and ‘2×’
means “double buffered”.
Table 6. Default Alternate Settings
Alternate
Setting
0
1
2
3
ep0
64 64
64
64
ep1out 0 64 bulk
64 int
64 int
ep1in
0 64 bulk
64 int
64 int
ep2
0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
ep4
0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
ep6
0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×)
ep8
0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
External FIFO Interface
Architecture
The FX1 slave FIFO architecture has eight 512-byte blocks in the
endpoint RAM that directly serve as FIFO memories, and are
controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of
these buffers depend on the USB transfer mode as described in
the section Organization on page 9.
In operation, some of the eight RAM blocks fill or empty from the
SIE, while the others are connected to the I/O transfer logic. The
transfer logic takes two forms: the GPIF for internally generated
control signals or the slave FIFO interface for externally
controlled transfers.
Figure 6. Endpoint Configuration
EP0 IN&OUT 64
64
64
EP1 IN 64
64
64
EP1 OUT 64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
EP2
64
64
EP4
64
64
EP2
64
64
EP4
64
64
EP2
64
64
EP4
64
64
EP6
64
64
EP8
64
64
1
EP6
64
64
64
64
2
EP6
1023
1023
3
EP2
64
64
EP2
64
64
EP2
64
64
64
64
64
64
64
64
EP6
64
64
EP8
64
64
4
EP6
64
64
64
64
5
EP6
1023
1023
6
EP2
1023
EP2
1023
EP2
1023
1023 1023 1023
EP6
64
64
EP8
64
64
7
EP6
64
64
64
64
8
EP6
1023
1023
9
EP2
64
64
64
EP6
64
EP2 EP2
1023
1023
1023
1023
64
1023
1023 1023
64
EP8 ^EP8
64
64 ₁₀₂₃
64
64
10 11 12
Document #: 38-08039 Rev. *F
Page 9 of 55
[+] Feedback