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| CY7C4801 Datasheet, PDF (9/23 Pages) Cypress Semiconductor – 256/512/1K/2K/4K/8K x9 x2 Double Sync FIFOs | |||
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CY7C4801/4811/4821
CY7C4831/4841/4851
Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLKA,WCLKB
DA0âDA8
(DB0âDB8)
tDS
tENS
WENA1(WENB1)
WENA2(WENB2)
(if applicable)
RCLKA(RCLKB)
EFA(EFB)
D0 (FIRSTVALID WRITE)
[15]
tFRL
tSKEW1
D1
tREF
D2
[16]
tA
D3
D4
tA
RENA1, RENA2
(RENB1,RENB2)
QA0 âQA8
(QB0âQB8)
OEA(OEB)
tOLZ
tOE
D0
D1
48X1â9
Notes:
15. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (EFA, EFB= LOW).
16. The first word is available the cycle after (EFA, EFB) goes HIGH, always.
Document #: 38-06005 Rev. **
Page 9 of 23
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