CY7C1355C_11 Datasheet, PDF (9/32 Pages) Cypress Semiconductor – 9-Mbit (256 K x 36 / 512 K x 18) Flow-through SRAM with NoBL Architecture

CY7C1355C, CY7C1357C
Pin Definitions
Name
A₀, A₁, A
BW_A, BW_B
BW_C, BW_D
WE
ADV/LD
CLK
CE₁
CE₂
CE₃
OE
CEN
ZZ
DQ_s
DQP_X
MODE
V_DD
V_DDQ
V_SS
TDO
TDI
I/O
Description
Input-
synchronous
Input-
synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge
of the CLK. A_[1:0] are fed to the two-bit burst counter.
Byte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
Input-
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
synchronous This signal must be asserted LOW to initiate a write sequence.
Input-
synchronous
Advance/load input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Input-
clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
Input-
synchronous
Input-
synchronous
Input-
synchronous
Input-
asynchronous
Chip enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE₂, and CE₃ to select/deselect the device.
Chip enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE₁ and CE₃ to select/deselect the device.
Chip enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE₁ and CE₂ to select/deselect the device.
Output enable, asynchronous input, active LOW. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device has been deselected.
Input-
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by
synchronous the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when required.
Input-
ZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep”
asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
I/O-
synchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous _{clock rise of the}
read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQ_s and DQP_X are placed in a tri-state condition.The
outputs are automatically tri-stated during the data portion of a write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
I/O-
synchronous
Input strap pin
Power supply
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ_s. During
write sequences, DQP_X is controlled by BW_X correspondingly.
Mode input. Selects the burst order of the device. When tied to Gnd selects linear burst
sequence. When tied to V_DD or left floating selects interleaved burst sequence.
Power supply inputs to the core of the device.
I/O power supply Power supply for the I/O circuitry.
Ground Ground for the device.
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
synchronous feature is not being utilized, this pin should be left unconnected. This pin is not available on
TQFP packages.
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
synchronous is not being utilized, this pin can be left floating or connected to V_DD through a pull-up
resistor. This pin is not available on TQFP packages.
Document Number: 38-05539 Rev. *H
Page 9 of 32
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