CY7C1344H Datasheet, PDF (9/15 Pages) Cypress Semiconductor – 2-Mbit (64K x 36) Flow-Through Sync SRAM

CY7C1344H
Switching Characteristics Over the Operating Range ^{[10, 11]}
133 MHz
100 MHz
Parameter
t_POWER
Clock
Description
V_DD(Typical) to the First Access^[12]
Min.
Max.
Min.
Max.
Unit
1
1
ms
t_CYC
Clock Cycle Time
t_CH
Clock HIGH
t_CL
Clock LOW
Output Times
7.5
10
ns
2.5
4.0
ns
2.5
4.0
ns
t_CDV
Data Output Valid after CLK Rise
t_DOH
t_CLZ
t_CHZ
Data Output Hold after CLK Rise
Clock to Low-Z^{[13, 14, 15]}
Clock to High-Z^{[13, 14, 15]}
t_OEV
t_OELZ
t_OEHZ
OE LOW to Output Valid
OE LOW to Output Low-Z^{[13, 14, 15]}
OE HIGH to Output High-Z^{[13, 14, 15]}
Set-up Times
6.5
8.0
ns
2.0
2.0
ns
0
0
ns
3.5
3.5
ns
3.5
3.5
ns
0
0
ns
3.5
3.5
ns
t_AS
Address Set-up before CLK Rise
1.5
2.0
ns
t_ADS
ADSP, ADSC Set-up before CLK Rise
1.5
2.0
ns
t_ADVS
ADV Set-up before CLK Rise
1.5
2.0
ns
t_WES
GW, BWE, BW_[A:D] Set-up before CLK Rise
1.5
2.0
ns
t_DS
Data Input Set-up before CLK Rise
1.5
2.0
ns
t_CES
Chip Enable Set-up
1.5
2.0
ns
Hold Times
t_AH
Address Hold after CLK Rise
0.5
0.5
ns
t_ADH
ADSP, ADSC Hold after CLK Rise
0.5
0.5
ns
t_WEH
GW, BWE, BW_[A:D] Hold after CLK Rise
0.5
0.5
ns
t_ADVH
ADV Hold after CLK Rise
0.5
0.5
ns
t_DH
Data Input Hold after CLK Rise
0.5
0.5
ns
t_CEH
Chip Enable Hold after CLK Rise
0.5
0.5
ns
Notes:
10. Timing reference level is 1.5V when V_DDQ = 3.3V and 1.25V when V_DDQ = 2.5V.
11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12. This part has a voltage regulator internally; t_POWER is the time that the power needs to be supplied above V_DD(minimum) initially before a Read or Write operation
can be initiated.
13. t_CHZ, t_CLZ, t_OELZ, and t_OEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
14. At any given voltage and temperature, t_OEHZ is less than t_OELZ and t_CHZ is less than t_CLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
Document #: 001-00211 Rev. *B
Page 9 of 15
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