CY7C1310JV18 Datasheet, PDF (9/26 Pages) Cypress Semiconductor – 18 Mbit QDR-II SRAM 2-Word Burst Architecture

CY7C1310JV18, CY7C1910JV18
CY7C1312JV18, CY7C1314JV18
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V_SS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with V_DDQ = 1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock (C/C) of the QDR-II. In single
clock mode, CQ is generated with respect to K and CQ is
generated with respect to K. The timing for the echo clocks is
shown in the Switching Characteristics on page 22.
DLL
These chips use a DLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the DLL is locked after 1024
cycles of stable clock. The DLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the DLL to lock to the
desired frequency. The DLL automatically locks 1024 clock
cycles after a stable clock is presented. The DLL may be
disabled by applying ground to the DOFF pin. When the DLL is
turned off, the device behaves in QDR-I mode (with one cycle
latency and a longer access time). For information refer to the
application note DLL Considerations in QDRII/DDRII.
Application Example
Figure 1 shows two QDR-II used in an application.
Figure 1. Application Example
SRAM #1
R = 250ohms
ZQ
Vt
RW B
D
PPW
SS S
CQ/CQ#
Q
R
A
# # # C C# K K#
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU _CLKIN/CLKIN#
or
Source K
ASIC)
Source K#
Delayed K
Delayed K#
R
R = 50ohms Vt = Vddq/2
SRAM #2
ZQ ^{R = 250ohms}
RWB
P PW
D
SSS
CQ/CQ#
Q
A
# # # C C# K K#
Vt
Vt
R
Document #: 001-43127 Rev. *A
Page 9 of 26
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