CY7C1310CV18 Datasheet, PDF (9/26 Pages) Cypress Semiconductor – 18-Mbit QDR-II™ SRAM 2-Word Burst Architecture

PRELIMINARY
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. During power-up, when the DOFF is tied HIGH, the
DLL gets locked after 1024 cycles of stable clock. The DLL can
also be reset by slowing or stopping the input clock K and K
for a minimum of 30 ns. However, it is not necessary for the
DLL to be specifically reset in order to lock the DLL to the
desired frequency. The DLL will automatically lock 1024 clock
cycles after a stable clock is presented. The DLL may be
disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device will behave in QDR-I mode (with one
cycle latency and a longer access time). For information refer
to the application note “DLL Considerations in QDRII/DDRII”.
Application Example^[1]
CY7C1310CV18
CY7C1910CV18
CY7C1312CV18
CY7C1314CV18
SRAM #1
R = 250οηµσ
ZQ
SRAM #4
ZQ ^{R = 250οηµσ}
Vt
R
RW B
CQ/CQ#
D
PPW
SS S
Q
A
## #
C C# K K#
RW B
CQ/CQ#
D
PPW
SS S
Q
A
## #
C C# K K#
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU _CLKIN/CLKIN#
or
Source K
ASIC)
Source K#
Vt
Vt
R
Delayed K
Delayed K#
R
Truth Table^{[2, 3, 4, 5, 6, 7]}
R = 50οηµσ Vt = Vddq/2
Operation
K
RPS
WPS
DQ
DQ
Write Cycle:
L-H
X
Load address on the rising edge of K clock;
input write data on K and K rising edges.
L D(A + 0) at K(t) ↑
D(A + 1) at K(t) ↑
Read Cycle:
L-H
L
Load address on the rising edge of K clock;
wait one and a half cycle; read data on C
and C rising edges.
X Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑
NOP: No Operation
L-H
H
H D=X
Q = High-Z
D=X
Q = High-Z
Standby: Clock Stopped
Stopped
X
X Previous State
Previous State
Notes:
1. The above application shows four QDR-II being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
Document #: 001-07164 Rev. *B
Page 9 of 26
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