CY28410-2 Datasheet, PDF (9/17 Pages) SpectraLinear Inc – Clock Generator for Intel Grantsdale Chipset

each other. Figure 4 is an example showing the relationship of
clocks coming up.
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. Power-down Assertion Timing Waveform
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tstable
<1.8nS
Tdrive_PW RDN#
<300µS, >200mV
Figure 4. Power-down Deassertion Timing Waveform
CY28410-2
Document #: 38-07747 Rev *.*
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