CY2305_12 Datasheet, PDF (9/21 Pages) Cypress Semiconductor – 3.3 V Zero Delay Clock Buffer

CY2305C
CY2309C
Switching Characteristics
Switching Characteristics Table for CY2305CSXC-1 and CY2309CSXC-1 Commercial Temperature devices. All parameters are
specified with loaded outputs.
Parameter
Description
Test Conditions
Min
t₁
Output frequency
30 pF load
10
10 pF load
10
t_DC
Output duty cycle ^[7] = t₂  t₁
Measured at 1.4 V, F_out > 50 MHz
40
Measured at 1.4 V, F_out  50 MHz
45
t₃
Rise time ^[7]
Measured between 0.8 V and 2.0 V
–
t₄
Fall time ^[7]
Measured between 0.8 V and 2.0 V
–
t₅
Output-to-output skew ^[7]
All outputs equally loaded
–
t_6A
Delay, REF rising edge to
CLKOUT rising edge ^[7]
Measured at V_DD/2
–
t_6B
t₇
t_J
t_LOCK
Delay, REF rising edge to
CLKOUT rising edge ^[7]
Measured at V_DD/2. Measured in
PLL Bypass mode, CY2309C
1
device only.
Device-to-device skew ^[7]
Measured at V_DD/2 on the
–
CLKOUT pins of devices
Cycle-to-cycle jitter, peak ^[7]
Measured at 66.67 MHz, loaded
–
outputs
PLL lock time ^[7]
Stable power supply, valid clock
–
presented on REF pin
Typ
Max Unit
–
100 MHz
133.33 MHz
50
60
%
50
55
%
–
2.25
ns
–
2.25
ns
–
200
ps
0
±350
ps
5
8.7
ns
0
700
ps
50
175
ps
–
1.0
ms
Note
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Document Number: 38-07672 Rev. *L
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