CY14MC256J_13 Datasheet, PDF (9/30 Pages) Cypress Semiconductor – 256-Kbit (32 K x 8) Serial (I2C) nvSRAM

CY14MC256J
CY14MB256J
CY14ME256J
endurance cycle per sleep command execution. A STORE
cycle starts only if a write to the SRAM has been performed
since the last STORE or RECALL cycle.
The nvSRAM enters into sleep mode as follows:
1. The Master sends a START command
2. The Master sends Control Registers Slave device ID with I²C
Write bit set (R/W = ’0’)
3. The Slave (nvSRAM) sends an ACK back to the Master
4. The Master sends Command Register address (0xAA)
5. The Slave (nvSRAM) sends an ACK back to the Master
6. The Master sends Command Register byte for entering into
Sleep mode
7. The Slave (nvSRAM) sends an ACK back to the Master
8. The Master generates a STOP condition.
Once in Sleep mode the device starts consuming I_ZZ current,
t_SLEEP time after SLEEP instruction is registered. The device is
not accessible for normal operations until it is out of sleep mode.
The nvSRAM wakes up after t_WAKE duration after the device
slave address is transmitted by the master.
Transmitting any of the two slave addresses wakes the nvSRAM
from Sleep mode. The nvSRAM device is not accessible during
t_SLEEP and t_WAKE interval, and any attempt to access the
nvSRAM device by the master is ignored and nvSRAM sends
NACK to the master. As an alternative method of determining
when the device is ready, the master can send read or write
commands and look for an ACK.
Write Protection (WP)
The WP pin is an active high pin and protects entire memory and
all registers from write operations. To inhibit all the write
operations, this pin must be held high. When this pin is high, all
memory and register writes are prohibited and address counter
is not incremented. This pin is internally pulled LOW and hence
can be left open if not used.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (V_CAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from V_CC to
charge the capacitor connected to the V_CAP pin. When the
voltage on the V_CC pin drops below V_SWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the V_CAP capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since the last
STORE or RECALL.
Note If a capacitor is not connected to V_CAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in Command Register on page 8. If AutoStore is
enabled without a capacitor on V_CAP pin, the device attempts an
AutoStore operation without sufficient charge to complete the
Store. This will corrupt the data stored in nvSRAM as well as the
serial number and it will unlock the SNL bit.
Figure 10 shows the proper connection of the storage capacitor
(V_CAP) for AutoStore operation. Refer to DC Electrical
Characteristics on page 18 for the size of the V_CAP.
Figure 10. AutoStore Mode
VCC
0.1 uF
VCC
VCAP
VSS
VCAP
Hardware STORE and HSB pin Operation
The HSB pin in CY14MX256J is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, the device conditionally
initiates a STORE operation after t_DELAY duration. An actual
STORE cycle starts only if a write to the SRAM has been
performed since the last STORE or RECALL cycle. Reads and
Writes to the memory are inhibited for t_STORE duration or as long
as HSB pin is LOW.
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t_HHHD) with standard output high
current and then remains HIGH by internal 100 k pull-up
resistor.
Note For successful last data byte STORE, a hardware STORE
should be initiated at least one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for t_LZHSB time after HSB pin returns HIGH.
Leave the HSB pin unconnected if not used.
Hardware RECALL (Power-Up)
During power-up, when V_CC crosses V_SWITCH, an automatic
RECALL sequence is initiated which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes t_FA time to complete and the
memory access is disabled during this time. HSB pin can be
used to detect the Ready status of the device.
Document Number: 001-65233 Rev. *G
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