MB9B160R Datasheet, PDF (87/158 Pages) Cypress Semiconductor – 32-Bit ARM® Cortex®-M4F FM4 Microcontroller

MB9B160R Series
Separate Bus Access Synchronous SRAM Mode
Parameter
Address delay time
MCSX delay time
Symbol
t_AV
t_CSL
t_CSH
Pin name
MCLK,
MAD[24:0]
MCLK,
MCSX[7:0]
MOEX delay time
Data set up
→MCLK↑ time
MCLK↑→
Data hold time
MWEX delay time
t_REL
MCLK,
MOEX
t_REH
t_DS
MCLK,
MADATA[15:0]
t_DH
MCLK,
MADATA[15:0]
t_WEL
t_WEH
MCLK,
MWEX
MDQM[1:0]
delay time
t_DQML
t_DQMH
MCLK,
MDQM[1:0]
MCLK↑→
Data output time
MCLK↑→
Data hold time
t_ODS
MCLK,
MADATA[15:0]
t_OD
MCLK,
MADATA[15:0]
Note: When the external load capacitance C_L = 30pF
MCLK
t_CYCLE
Conditions
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
V_CC ≥ 4.5V
V_CC < 4.5V
(V_CC = 2.7V to 5.5V, V_SS = 0V)
Value
Min
Max
Unit
9
1
ns
12
9
1
ns
12
9
1
ns
12
9
1
ns
12
9
1
ns
12
19
-
ns
37
0
-
ns
1
1
1
1
MCLK+1
1
9
ns
12
9
ns
12
9
ns
12
9
ns
12
MCLK+18
ns
MCLK+24
18
ns
24
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
t_CSL
t_AV
Address
t_REL
t_DQML
t_CSH
t_AV
t_REH
t_DQMH
Address
t_DQML
MWEX
MADATA[15:0]
Document Number: 002-04918 Rev.*A
t_DS
t_DH
RD
t_WEL
Invalid
t_ODS
WD
t_DQMH
t_WEH
t_OD
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