FM25040B_13 Datasheet, PDF (8/14 Pages) Cypress Semiconductor – 4Kb Serial 5V F-RAM Memory

FM25040B - 4Kb 5V SPI F-RAM
CS
SCK
SI
SO
012345670123456 701234567
7
op-code
Byte Address
Data
0 0 0 0 A0 1 07 6 5 4 3 2 1 07 6 5 4 3 2 1 0
0
MSB
LSB MSB
LSB
Hi-Z
Figure 9. Memory Write
CS
SCK
0123456701 23456 701 234567
7
op-code
Byte Address
SI
0 0 0 0 A0 1 17 6 5 4 3 2 1 0
MSB
LSB
Data Out
SO
Hi-Z
76543 210
0
MSB
LSB LSB
Figure 10. Memory Read
Endurance
Internally, a F-RAM operates with a read and restore
mechanism. Therefore, endurance cycles are applied
for each access: read or write. The F-RAM
architecture is based on an array of rows and
columns. Each access causes a cycle for an entire
row. In the FM25040B, a row is 64 bits wide. Every
8-byte boundary marks the beginning of a new row.
Endurance can be optimized by ensuring frequently
accessed data is located in different rows.
Regardless, F-RAM read and write endurance is
effectively unlimited at the 20MHz clock speed.
Even at 2000 accesses per second to the same row, 15
years time will elapse before 10¹² endurance cycles
occur.
Document Number: 001-86145 Rev. *A
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