CYRS1543AV18 Datasheet, PDF (8/32 Pages) Cypress Semiconductor – 72-Mbit QDR® II+ SRAM Four-Word Burst

CYRS1543AV18
CYRS1545AV18
Functional Overview
The CYRS1543AV18, CYRS1545AV18 are synchronous
pipelined burst SRAMs with a read port and a write port. The read
port is dedicated to read operations and the write port is
dedicated to write operations. Data flows into the SRAM through
the write port and flows out through the read port. These devices
multiplex the address inputs to minimize the number of address
pins required. By having separate read and write ports, the
QDR II completely eliminates the need to turnaround the data
bus and avoids any possible data contention, thereby simplifying
system design. Each access consists of four 18-bit data transfers
in the case of CYRS1543AV18, and four 36-bit data transfers in
the case of CYRS1545AV18 in two clock cycles.
This device operates with a read latency of two cycles when
DOFF pin is tied HIGH. When DOFF pin is set LOW or connected
to V_SS then device behaves in QDR I mode with a read latency
of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input timing is referenced from the rising
edge of the input clocks (K and K) and all output timing is
referenced to the output clocks (K and K).
All synchronous data inputs (D_[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q_[x:0]) pass through output registers controlled by the
rising edge of the output clocks (K and K).
All synchronous control (RPS, WPS, BWS_[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CYRS1543AV18 is described below. The same basic
descriptions also apply to CYRS1545AV18.
Read Operations
The CYRS1543AV18 is organized internally as four arrays of
1 M × 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q_[17:0] using K as the output timing reference. On the subsequent
rising edge of Kb, the next 18-bit data word is drive onto the
QQ_[17:0]. This process continues until all four 18-bit data words
have been driven out onto Q_[17:0]. The requested data is valid
0.45 ns from the rising edge of the output clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the output
clocks (K and K).
When the read port is deselected, the CYRS1543AV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tri-states the outputs following the next
rising edge of the positive input clock (K). This allows for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D_[17:0] is latched and stored into
the lower 18-bit write data register, provided BWS_[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D_[17:0] is also stored
into the write data register, provided BWS_[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The
72 bits of data are then written into the memory array at the
specified location. Therefore, write accesses to the device can
not be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second write request. Write
accesses can be initiated on every other rising edge of the
positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CYRS1543AV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS₀ and
BWS₁, which are sampled with each set of 18-bit data words.
Asserting the appropriate BWS input during the data portion of a
write latches the data being presented and writes it into the
device. Deasserting the BWS input during the data portion of a
write allows the data stored in the device for that byte to remain
unaltered. This feature can be used to simplify read, modify, or
write operations to a byte write operation.
Concurrent Transactions
The read and write ports on the CYRS1543AV18 operate
independently of one another. As each port latches the address
inputs on different clock edges, you can read or write to any
location, regardless of the transaction on the other port. If the
ports access the same location when a read follows a write in
successive clock cycles, the SRAM delivers the most recent
information associated with the specified address location. This
includes forwarding data from a write cycle that was initiated on
the previous K clock rise.
Read access and write access must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports are deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations can not be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
can not be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in alter-
nating read or write operations being initiated, with the first
access being a read.
Document Number: 001-60007 Rev. *H
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