CY8C20X66 Datasheet, PDF (8/34 Pages) Cypress Semiconductor – CapSense™ Applications

CY8C20x46, CY8C20x66
Pin Information
This section describes, lists, and illustrates the CY8C20x46/CY8C20x66 PSoC device pins and pinout configurations.
The CY8C20x46/CY8C20x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES
are not capable of Digital IO.
16-Pin Part Pinout
Table 2. 16-Pin QFN Part Pinout⁽²⁾
Pin
No.
Type
Name
Digital Analog
Description
1
IO
I
P2[5] Crystal output (XOut).
2
IO
I
P2[3] Crystal input (XIn).
3
IOHR
I
P1[7] I2C SCL, SPI SS.
4
IOHR
I
P1[5] I2C SDA, SPI MISO.
5
IOHR
6
IOHR
I
P1[3] SPI CLK.
I
P1[1] ISSP CLK⁽¹⁾, I2C SCL, SPI MOSI.
7
Power
Vss Ground connection.
8
IOHR
I
P1[0] ISSP DATA⁽¹⁾, I2C SDA, SPI CLK.
9
IOHR
I
P1[2]
10 IOHR
I
P1[4] Optional external clock (EXTCLK)
11
Input
XRES Active high external reset with
internal pull down.
12
IOH
I
P0[4]
13
Power
Vdd Supply voltage.
14
IOH
I
P0[7]
15
IOH
I
P0[3] Integrating input.
Figure 2. CY8C20246, CY8C20266 16-Pin PSoC Device
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
1
12
2
QFN
(Top View)
11
3
10
4
9
P0[4], AI
XRES
P1[4], EXTCLK, AI
P1[2], AI
16
IOH
I
P0[1] Integrating input.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
1. These are the ISSP pins, which are not High Z at POR (Power On Reset).
2. During power up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues.
Document Number: 001-12696 Rev. *C
Page 8 of 34
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