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CY7C344B Datasheet, PDF (8/16 Pages) Cypress Semiconductor – 32-Macrocell MAX EPLD | |||
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USE ULTRA37000TM FOR
ALL NEW DESIGNS
CY7C344B
Typical Internal Switching Characteristics Over Operating Range[7]
7C344-15 7C344-20 7C344-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
tIN
Dedicated Input Pad and Buffer Delay
Comâl/Ind
4
5
7 ns
Mil
4
5
7
tIO
I/O Input Pad and Buffer Delay
Comâl/Ind
4
5
7 ns
Mil
4
5
7
tEXP
Expander Array Delay
Comâl/Ind
8
Mil
8
10
15 ns
10
15
tLAD
Logic Array Data Delay
Comâl/Ind
7
Mil
7
9
10 ns
9
10
tLAC
Logic Array Control Delay
Comâl/Ind
5
7
7 ns
Mil
5
7
7
tOD
Output Buffer and Pad Delay
tZX
Output Buffer Enable Delay[27]
Comâl/Ind
4
Mil
4
Comâl/Ind
7
Mil
7
5
5 ns
5
5
8
11 ns
8
11
tXZ
Output Buffer Disable Delay
Comâl/Ind
7
Mil
7
8
11 ns
8
11
tRSU
Register Set-Up Time Relative to Clock Signal Comâl/Ind 5
5
8
ns
at Register
Mil
5
5
8
tRH
Register Hold Time Relative to Clock Signal at Comâl/Ind 7
Register
Mil
7
9
12
ns
9
12
tLATCH
Flow-Through Latch Delay
Comâl/Ind
1
1
3 ns
Mil
1
1
3
tRD
tCOMB
Register Delay
Transparent Mode Delay[28]
Comâl/Ind
1
1
1 ns
Mil
1
1
1
Comâl/Ind
1
1
3 ns
Mil
1
1
3
tCH
Clock HIGH Time
Comâl/Ind 6
7
8
ns
Mil
6
7
8
tCL
Clock LOW Time
Comâl/Ind 6
7
8
ns
Mil
6
7
8
tIC
Asynchronous Clock Logic Delay
Comâl/Ind
7
Mil
7
8
10 ns
8
10
tICS
Synchronous Clock Delay
Comâl/Ind
1
2
3 ns
Mil
1
2
3
tFD
Feedback Delay
Comâl/Ind
1
1
1 ns
Mil
1
1
1
tPRE
Asynchronous Register Preset Time
Comâl/Ind
5
6
9 ns
Mil
5
6
9
Notes:
27. Sample tested only for an output change of 500 mV.
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial
operation.
Document #: 38-03006 Rev. *A
Page 8 of 16
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