CY7C199C-15VIT Datasheet, PDF (8/13 Pages) Cypress Semiconductor – 256K (32K x 8) Static RAM

Timing Waveforms (continued)
Write Cycle No. 2 (CE Controlled)^{[14, 16, 17]}
Address
CE
t_SA
WE
Data In/Out
High Z
CY7C199C
t_WC
t_SCE
t_HA
t_AW
t_SD
t_HD
Data-In Valid
High Z
Write Cycle No. 3 (WE Controlled, OE Low)^[18]
Address
CE
WE
Data
In/Out
t_SA
Undefined
see footnotes
t _WC
t_SCE
t_AW
t_PWE
t_HZWE
t_SD
Data-In Valid
Notes:
16. This cycle is CE controlled.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18. The cycle is WE controlled, OE LOW. The minimum write cycle time is the sum of t_HZWE and t_SD.
t_HA
t_HD
t_LZWE
Undefined
See Footnotes
Document #: 38-05408 Rev. *C
Page 8 of 13
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