CY7C15632KV18_12 Datasheet, PDF (8/30 Pages) Cypress Semiconductor – 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C15632KV18
Application Example
Figure 2 shows two QDR II+ used in an application.
Figure 2. Application Example
RQ = 250 ohms
ZQ
Vt
SRAM #1 _CQ/CQ
D
Q
D
R
A RPS WPS BWS K K
A
SRAM #2
RQ = 250 ohms
ZQ
CQ/CQ
Q
RPS WPS BWS K ^K
DATA IN
DATA OUT
Address
BUS MASTER ^RPS
(CPU or ASIC) ^WPS
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
Source K
Source K
R
R
Vt
Vt
R
R = 50ohms, Vt = VDDQ/2
Document Number: 001-54932 Rev. *F
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