CY7C1346F Datasheet, PDF (8/16 Pages) Cypress Semiconductor – 2-Mbit (64K x 36) Pipelined Sync SRAM

CY7C1346F
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V_DD Relative to GND........ –0.5V to +4.6V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Ambient
Range Temperature
V_DD
V_DDQ
DC Voltage Applied to Outputs
inThree-State ...................................... –0.5V to V_DDQ + 0.5V
Commercial 0°C to +70°C 3.3V –5%/+10% 3.3V –5%
to V_DD
DC Input Voltage....................................–0.5V to V_DD + 0.5V
Electrical Characteristics Over the Operating Range ^{[8, 9]}
Parameter
Description
Test Conditions
Min.
V_DD
V_DDQ
V_OH
V_OL
V_IH
V_IL
I_X
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage^[8]
Input LOW Voltage^[8]
Input Load Current
except ZZ and MODE
V_DDQ = 3.3V, V_DD = Min., I_OH = –4.0 mA
V_DDQ = 3.3V, V_DD = Min., I_OL = 8.0 mA
V_DDQ = 3.3V
V_DDQ = 3.3V
GND ≤ V_I ≤ V_DDQ
3.135
3.135
2.4
2.0
–0.3
–5
Input Current of MODE Input = V_SS
–30
Input = V_DD
Input Current of ZZ
Input = V_SS
–5
Input = V_DD
I_OZ
Output Leakage Current GND ≤ V_I ≤ V_DDQ, Output Disabled
–5
I_DD
V_DD Operating Supply V_DD = Max., I_OUT = 0 mA, 6-ns cycle,166 MHz
Current
f = f_MAX = 1/t_CYC
7.5-ns cycle,133MHz
10-ns cycle, 100 MHz
I_SB1
Automatic CS
V_DD = Max, Device
6-ns cycle,166 MHz
Power-down
Current—TTL Inputs
Deselected, V_IN ≥ V_IH or
V_IN ≤ V_IL
f = f_MAX = 1/t_CYC
7.5-ns cycle,133 MHz
10-ns cycle, 100 MHz
I_SB2
Automatic CS
V_DD = Max, Device
All speeds
Power-down
Deselected, V_IN ≤ 0.3V or
Current—CMOS Inputs V_IN > V_DDQ – 0.3V, f = 0
I_SB3
Automatic CS
V_DD = Max, Device
6-ns cycle,166 MHz
Power-down
Deselected, or V_IN ≤ 0.3V _{7.5-ns cycle,133 MHz}
Current—CMOS Inputs or
V_IN > V_DDQ – 0.3V
10-ns cycle, 100 MHz
f = f_MAX = 1/t_CYC
I_SB4
Automatic CS
V_DD = Max, Device
All speeds
Power-down
Deselected, V_IN ≥ V_IH or
Current—TTL Inputs V_IN ≤ V_IL, f = 0
Notes:
8. Overshoot: V_IH(AC) < V_DD +1.5V (Pulse width less than t_CYC/2), undershoot: V_IL(AC) > –2V (Pulse width less than t_CYC/2).
9. T_Power-up: Assumes a linear ramp from 0V to V_DD(min.) within 200 ms. During this time V_IH < V_DD and V_DDQ < V_DD.
Max.
3.6
V_DD
0.4
V_DD + 0.3V
0.8
5
5
30
5
240
225
205
100
90
80
40
85
75
65
45
Unit
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Document #: 38-05384 Rev. *B
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