CY7C1340F Datasheet, PDF (8/17 Pages) Cypress Semiconductor – 4-Mb (128K x 32) Pipelined DCD Sync SRAM

CY7C1340F
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883,Method 3015)
Latch -up Current..................................................... >200 mA
Storage Temperature .................................... –65°C to +150°
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V_DD Relative to GND........ –0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State ..................................... –0.5V to V_DDQ + 0.5V
DC Input Voltage....................................–0.5V to V_DD + 0.5V
Current into Outputs (LOW) .........................................20 mA
Operating Range
Ambient
Range Temperature (T_A)
V_DD
V_DDQ
Commercial 0°C to +70°C 3.3V −5%/+10% 2.5V−5%
Industrial –40°C to +85°C
to V_DD
Electrical Characteristics Over the Operating Range^{[8, 9]}
Parameter
Description
Test Conditions
Min. Max. Unit
V_DD
V_DDQ
V_OH
V_OL
V_IH
V_IL
I_X
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage^[8]
Input LOW Voltage^[8]
Input Load Current except ZZ
and MODE
V_DDQ = 3.3V, V_DD = Min., I_OH = –4.0 mA
V_DDQ = 2.5V, V_DD = Min., I_OH = –2.0 mA
V_DDQ = 3.3V, V_DD = Min., I_OL = 8.0 mA
V_DDQ = 2.5V, V_DD = Min., I_OL = 2.0 mA
V_DDQ = 3.3V
V_DDQ = 2.5V
V_DDQ = 3.3V
V_DDQ = 2.5V
GND ≤ V_I ≤ V_DDQ
3.135 3.6
V
2.375 V_DD
V
2.4
V
2.0
V
0.4
V
0.4
V
2.0 V_DD + 0.3V V
1.7 V_DD + 0.3V V
–0.3
0.8
V
–0.3
0.7
V
–5
5
µA
Input Current of MODE
Input = V_SS
–30
µA
Input = V_DD
5
µA
Input Current of ZZ
Input = V_SS
–5
µA
Input = V_DD
30
µA
I_OZ
Output Leakage Current
GND ≤ V_I ≤ V_DDQ, Output Disabled
–5
5
µA
I_DD
V_DD Operating Supply Cur- V_DD = Max., I_OUT = 0 mA,
4-ns cycle, 250 MHz
rent
f = f_MAX = 1/t_CYC
4.4-ns cycle, 225 MHz
325
mA
290
mA
5-ns cycle, 200 MHz
265
mA
6-ns cycle, 166 MHz
240
mA
7.5-ns cycle, 133 MHz
225
mA
10-ns cycle, 100 MHz
205
mA
I_SB1
Automatic CE
Power-down
Current—TTL Inputs
V_DD = Max., Device Deselected, 4-ns cycle, 250 MHz
V_IN ≥ V_IH or V_IN ≤ V_IL, f = f_MAX = _{4.4-ns cycle, 225 MHz}
1/t_CYC
5-ns cycle, 200 MHz
120
mA
115
mA
110
mA
6-ns cycle, 166 MHz
100
mA
7.5-ns cycle, 133 MHz
90
mA
10-ns cycle, 100 MHz
80
mA
Shaded areas contain advance information.
Notes:
8. Overshoot: V_IH(AC) < V_DD +1.5V (Pulse width less than t_CYC/2), undershoot: V_IL(AC)> –2V (Pulse width less than t_CYC/2).
9. T_Power-up: Assumes a linear ramp from 0v to V_DD(min.) within 200 ms. During this time V_IH < V_DD and V_DDQ < V_DD.
Document #: 38-05219 Rev. *A
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