CY7C056V_12 Datasheet, PDF (8/27 Pages) Cypress Semiconductor – 3.3 V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static RAM

CY7C056V
CY7C057V
Electrical Characteristics Over the Operating Range^[8]
Parameter
Description
V_OH
Output HIGH voltage
(V_DD = Min., I_OH = –4.0 mA)
V_OL
Output LOW voltage
(V_DD = Min., I_OL = +4.0 mA)
V_IH
Input HIGH voltage
V_IL
Input LOW voltage
I_OZ
Output leakage current
I_CC
Operating current (V_DD = Max.,
Commercial
I_OUT = 0 mA) output disabled
Industrial
I_SB1
Standby current (Both ports TTL level Commercial
and deselected)
f = f_MAX
Industrial
I_SB2
Standby current (One port TTL
Commercial
level and deselected)
f = f_MAX
Industrial
I_SB3
Standby current (Both ports CMOS Commercial
level and deselected) f =0
Industrial
I_SB4
Standby current (One Port CMOS
level and deselected) f = f_MAX[9]
Commercial
Industrial
CY7C056V
CY7C057V
-12
-15
Min Typ Max Min Typ
2.4
–
2.4
–
0.4
–
–
2.0
–
2.0
–
0.8
–
–10
10 –10
250 385
240
–
265
55
75
50
–
65
180 240
175
–
–
–
190
0.01 1
0.01
–
0.01
160 210
155
–
170
Capacitance^[10]
Parameter
Description
Test Conditions
Max
C_IN
C_OUT
Input capacitance
T_A = 25 C, f = 1 MHz,
10
Output capacitance
V_DD = 3.3 V
10
Max Unit
–
V
0.4
V
–
V
0.8
V
10
A
360 mA
385 mA
70
mA
95
mA
230 mA
255 mA
1
mA
1
mA
200 mA
215 mA
Unit
pF
pF
Notes
8. Deselection for a port occurs if CE₀ is HIGH or if CE₁ is LOW.
9. f_MAX = 1/t_RC = All inputs cycling at f = 1/t_RC (except Output Enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I_SB3.
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06055 Rev. *F
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