CY7C027V_09 Datasheet, PDF (8/18 Pages) Cypress Semiconductor – 3.3V 32K/64K x 16/18 Dual-Port Static RAM

CY7C027V/027VN/027AV/028V
CY7C037V/037AV/038V
Switching Characteristics Over the Operating Range^[6](continued)
Parameter
Description
t_HD
Data Hold From Write End
t_HZWE[9, ^10]
R/W LOW to High Z
t_LZWE[9 ^,10]
R/W HIGH to Low Z
t_WDD[36]
Write Pulse to Data Delay
t_DDD[36]
Write Data Valid to Read Data Valid
Busy Timing^[11]
t_BLA
BUSY LOW from Address Match
t_BHA
BUSY HIGH from Address Mismatch
t_BLC
BUSY LOW from CE LOW
t_BHC
BUSY HIGH from CE HIGH
t_PS
Port Setup for Priority
t_WB
R/W HIGH after BUSY (Slave)
t_WH
R/W HIGH after BUSY HIGH (Slave)
t_BDD[13]
BUSY HIGH to Data Valid
Interrupt Timing^[11]
t_INS
INT Set Time
t_INR
INT Reset Time
Semaphore Timing
t_SOP
t_SWRD
t_SPS
t_SAA
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
CY7C027V/027VN/027AV/028V/
CY7C037V/037AV/038V
-15
-20
-25
Unit
Min Max Min Max Min Max
0
0
0
ns
10
12
15
ns
3
3
3
ns
30
40
50
ns
25
30
35
ns
15
20
20
ns
15
20
20
ns
15
20
20
ns
15
16
17
ns
5
5
5
ns
0
0
0
ns
13
15
17
ns
15
20
25
ns
15
20
20
ns
15
20
20
ns
10
10
12
ns
5
5
5
ns
5
5
5
ns
15
20
25
ns
Data Retention Mode
Timing
The
CY7C027V/027VN/027AV/028V
and
CY7037V/037AV/038V are designed with battery backup in
mind. Data retention voltage and supply current are guaranteed
over temperature. The following rules ensure data retention:
1. Chip enable (CE) must be held HIGH during data retention, within
V_CC to V_CC – 0.2V.
2. CE must be kept between V_CC – 0.2V and 70% of V_CC during
the power up and power down transitions.
3. The RAM can begin operation >t_RC after V_CC reaches the mini-
mum operating voltage (3.0 volts).
Data Retention Mode
V_CC
3.0V
V_CC > 2.0V
3.0V
t_RC
CE
V_CC to V_CC – 0.2V
VIH
Parameter
Test Conditions^[14] Max Unit
ICC_DR1
At VCC_DR = 2V
50
μA
Notes
11. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 waveform.
12. Test conditions used are Load 1.
13. t_BDD is a calculated parameter and is the greater of t_WDD–t_PWE (actual) or t_DDD–t_SD (actual).
14. CE = V_CC, V_in = GND to V_CC, T_A = 25° C. This parameter is guaranteed but not tested.
Document #: 38-06078 Rev. *B
Page 8 of 18
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