CY7B993V_11 Datasheet, PDF (8/18 Pages) Cypress Semiconductor – High Speed Multi Phase PLL Clock Buffer

RoboClock^
CY7B993V, CY7B994V
Figure 3. Typical Outputs with FB Connected to a Zero-Skew Output^[]
1F[1:0]
2F[1:0]
(N/A)
(N/A)
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
FBInput
REFInput
3F[1:0]
4F[1:0]
LL
–8t_U
LM
–7t_U
LH
–6t_U
(N/A)
(N/A)
–4t_U
–3t_U
(N/A)
(N/A)
MM
(N/A)
(N/A)
(N/A)
(N/A)
HL
HM
HH
–2t_U
–1t_U
0t _U
+1t _U
+2t _U
+3t _U
+4t _U
+6t _U
+7t _U
+8t _U
Output Disable Description
The feedback Divide and Phase Select Matrix Bank has two
outputs, and each of the four Divide and Phase Select Matrix
Banks have four outputs. The outputs of each bank can be
independently put into a HOLD-OFF or high impedance state.
The combination of the OUTPUT_MODE and DIS[1:4]/FBDIS
inputs determines the clock outputs’ state for each bank. When
the DIS[1:4]/FBDIS is LOW, the outputs of the corresponding
bank is enabled. When the DIS[1:4]/FBDIS is HIGH, the outputs
for that bank is disabled to a high impedance (High Z) or
HOLD-OFF state depending on the OUTPUT_MODE input.
Table 6 defines the disabled output functions.
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a maximum
of six output clock cycles from the time when the disable input
(DIS[1:4]/FBDIS) is HIGH. When disabled to the HOLD-OFF
state, non-inverting outputs are driven to a logic LOW state on
its falling edge. Inverting outputs are driven to a logic HIGH state
on its rising edge. This ensures the output clocks are stopped
without glitch. When a bank of outputs is disabled to High Z state,
the respective bank of outputs go High Z immediately.
Table 6. DIS[1:4]/FBDIS Pin Functionality
OUTPUT_MODE
HIGH/LOW
HIGH
LOW
MID
DIS[1:4]/FBDIS
LOW
HIGH
HIGH
X
Output Mode
ENABLED
HIGH Z
HOLD-OFF
FACTORY TEST
Note
4. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
Document #: 38-07127 Rev. *J
Page 8 of 18
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