CY62138EV30_11 Datasheet, PDF (8/12 Pages) Cypress Semiconductor – 2 Mbit (256K x 8) MoBL Static RAM

CY62138EV30 MoBL^®
Switching Waveforms (continued)
Figure 5. Write Cycle No. 2 CE Controlled ^{[24, 25]}
ADDRESS
CE
WE
t_WC
t_SCE
t_HA
t_SA
t_AW
t_PWE
OE
DATA I/O
ADDRESS
CE
WE
DATA I/O
Truth Table
CE
WE
H^[27]
X
L
H
L
H
L
L
t_SD
t_HD
DATA_IN VALID
Figure 6. Write Cycle No. 3 : WE Controlled, OE LOW ^[25]
t_WC
t_SA
NOTE 26
t_HZWE
t_SCE
t_AW
t_PWE
t_SD
DATA_IN VALID
t_HA
t_HD
t_LZWE
OE
Inputs/Outputs
X High Z
L
Data out (I/O₀–I/O₇)
H High Z
X Data in (I/O₀–I/O₇)
Mode
Deselect/power-down
Read
Output disabled
Write
Power
Standby (I_SB)
Active (I_CC)
Active (I_CC)
Active (I_CC)
Notes
24. Data I/O is high impedance if OE = V_IH
25. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
26. During this period, the I/Os are in output state and input signals should not be applied.
27. Chip enable (CE) must be tied to CMOS levels to meet the I_SB1 / I_SB2 / I_CCDR specification. Other inputs can be left floating.
Document #: 38-05577 Rev. *C
Page 8 of 12
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