CY62137FV18_09 Datasheet, PDF (8/11 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

Switching Waveforms (continued)
Figure 8 shows the read cycle No.1 that is WE controlled, OE LOW. ^[20]
Figure 8. Write Cycle No. 3
ADDRESS
CE
BHE/BLE
t_SA
WE
t_WC
t_SCE
t_BW
t_AW
t_PWE
DATA IO
NOTE 21
t_HZWE
t_SD
DATA_IN
Figure 9 shows the read cycle No.1 that is BHE/BLE controlled, OE LOW. ^[20]
Figure 9. Write Cycle No. 4
t_WC
ADDRESS
CE
BHE/BLE
WE
DATA IO
t_SA
NOTE 21
t_HZWE
t_SCE
t_AW
t_BW
t_PWE
t_SD
DATA_IN
CY62137FV18 MoBL^®
t_HA
t_HD
t_LZWE
t_HA
t_HD
t_LZWE
Document #: 001-08030 Rev. *E
Page 8 of 11
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