CY62136V Datasheet, PDF (8/13 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)^{[12, 17, 18]}
ADDRESS
CE
WE
t_SA
t_WC
t_AW
t_PWE
BHE/BLE
OE
DATA I/O
NOTE 19
t_HZOE
t_BW
t_SD
DATA_IN VALID
Write Cycle No. 2 (CE Controlled)^{[12, 17, 18]}
ADDRESS
CE
WE
BHE/BLE
t_WC
t_SCE
t_SA
t_AW
t_PWE
t_BW
OE
DATA I/O
NOTE 19
t_HZOE
t_SD
DATA_IN VALID
Notes:
17. Data I/O is high impedance if OE = V_IH
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
19. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05087 Rev. *D
CY62136V MoBL^®
t_HA
t_HD
t_HA
t_HD
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