CY2DL1504_1105 Datasheet, PDF (8/14 Pages) Cypress Semiconductor – 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input

Figure 7. Output-to-output and Device-to-device Skew
Q_X
Q_X#
Device 1
Q_Y
Q_Y#
Q_Z
Device 2
Q_Z#
t_SK1
t_{SK1 D}
Figure 8. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
CLK_EN
IN
IN#
Q_X
Q_X#
Offset Frequency
f1
f2
RMS Jitter ∝ Area Under the Masked Phase Noise Plot
Figure 9. Output Rise/Fall Time
Q_X
80% 80%
20%
20%
V_PP
Q_X #
t_R
t_F
Figure 10. Synchronous Clock Enable Timing
t_SOD
tPD
t_SOE
CY2DL1504
Document Number: 001-56312 Rev. *F
Page 8 of 14
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