CY22801_11 Datasheet, PDF (8/23 Pages) Cypress Semiconductor – Universal Programmable Clock Generator (UPCG) Integrated phase-locked loop (PLL)

CY22801
Input Load Capacitors
XCapSrc bit in 12H register selects the source of Input load
capacitance. This will be set by CyClockRT software based on
selected configuration.
Input load capacitors allow you to set the load capacitance of the
CY22801 to match the input load capacitance from a crystal. The
value of the input load capacitors is determined by 8 bits in a
programmable register [13H]. Total load capacitance is
determined by the formula:
CapLoad = (C_L– C_BRD – C_CHIP)/0.09375 pF
where:
■ C_L = specified load capacitance of your crystal.
■ C_BRD = the total board capacitance, due to external capacitors
and board trace capacitance. In CyClocksRT, this value
defaults to 2 pF.
■ C_CHIP = 6 pF.
■ 0.09375 pF = the step resolution available due to the 8-bit
register.
In CyclocksRT, only the crystal capacitance (C_L) is specified.
C_CHIP is set to 6 pF and C_BRD defaults to 2 pF. If your board
capacitance is higher or lower than 2 pF, the formula given earlier
is used to calculate a new CapLoad value and programmed into
register 13H.
In CyClocksRT, enter the crystal capacitance (C_L). The value of
CapLoad is determined automatically and programmed into the
CY22801. Through the SDAT and SCLK pins, the value can be
adjusted up or down if your board capacitance is greater or less
than 2 pF. For an external clock source, CapLoad defaults to 0.
See Table 8 on page 9 for CapLoad bit locations and values.
The input load capacitors are placed on the CY22801 die to
reduce external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency shift
that occurs when nonlinear load capacitance is affected by load,
bias, supply, and temperature changes.
PLL Frequency, Q Counter [42H(6..0)]
The first counter is known as the Q counter. The Q counter
divides REF by its calculated value. Q is a 7 bit divider with a
maximum value of 127 and minimum value of 0. The primary
value of Q is determined by 7 bits in register 42H (6..0), but 2 is
added to this register value to achieve the total Q, or Q_total. Q_total
is defined by the formula:
Q_total = Q + 2
The minimum value of Q_total is 2. The maximum value of Q_total is
129. Register 42H is defined in the table.
Stable operation of the CY22801 cannot be guaranteed if
REF/Q_total falls below 250 kHz. Q_total bit locations and values are
defined in Table 9 on page 9.
PLL Frequency, P Counter [40H(1..0)], [41H(7..0)],
[42H(7)]
The next counter definition is the P (product) counter. The P
counter is multiplied with the (REF/Q_total) value to achieve the
VCO frequency. The product counter, defined as P_total, is made
up of two internal variables, PB and PO. The formula for
calculating P_total is:
P_total = (2(PB + 4) + PO)
PB is a 10-bit variable, defined by registers 40H(1:0) and
41H(7:0). The 2 LSBs of register 40H are the two MSBs of
variable PB. Bits 4..2 of register 40H are used to determine the
charge pump settings. The three MSBs of register 40H are
preset and reserved and cannot be changed. PO is a single bit
variable, defined in register 42H(7). This allows for odd numbers
in P_total.
The remaining seven bits of 42H are used to define the
Q counter, as shown in Table 9.
The minimum value of P_total is 8. The maximum value of P_total is
2055. To achieve the minimum value of P_total, PB and PO should
both be programmed to 0. To achieve the maximum value of
P_total, PB should be programmed to 1023, and PO should be
programmed to 1.
Stable operation of the CY22150 cannot be guaranteed if the
value of (P_total*(REF/Q_total)) is above 400 MHz or below
100 MHz.
PLL Post Divider Options [0CH(7..0)], [47H(7..0)]
The output of the VCO is routed through two independent
muxes, then to two divider banks to determine the final clock
output frequency. The mux determines if the clock signal feeding
into the divider banks is the calculated VCO frequency or REF.
There are two select muxes (DIV1SRC and DIV2SRC) and two
divider banks (Divider Bank 1 and Divider Bank 2) used to
determine this clock signal. The clock signal passing through
DIV1SRC and DIV2SRC is referred to as DIV1CLK and
DIV2CLK, respectively.
The divider banks have four unique divider options available: /2,
/3, /4, and /DIVxN. DIVxN is a variable that can be independently
programmed (DIV1N and DIV2N) for each of the two divider
banks. The minimum value of DIVxN is 4. The maximum value
of DIVxN is 127. A value of DIVxN below 4 is not guaranteed to
work properly.
DIV1SRC is a single bit variable, controlled by register 0CH. The
remaining seven bits of register 0CH determine the value of post
divider DIV1N.
DIV2SRC is a single bit variable, controlled by register 47H. The
remaining seven bits of register 47H determine the value of post
divider DIV2N.
Register 0CH and 47H are defined in Table 10.
Charge Pump Settings [40H(2..0)]
The correct pump setting is important for PLL stability. Charge
pump settings are controlled by bits (4..2) of register 40H, and
are dependent on internal variable PB (see “PLL Frequency, P
Counter[40H(1..0)], [41H(7..0)], [42H(7)]”). Table 11 on page 9
summarizes the proper charge pump settings, based on Ptotal.
See Table 12 on page 9 for register 40H bit locations and values.
Document #: 001-15571 Rev. *E
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