CY22150_11 Datasheet, PDF (8/18 Pages) Cypress Semiconductor – One-PLL General-Purpose Flash-Programmable and I2C Programmable Clock Generator

CY22150
Clock Output Settings: CLKSRC – Clock Output
Crosspoint Switch Matrix [44H(7..0)], [45H(7..0)],
[46H(7..6)]
Every clock output can be defined to come from one of seven
unique frequency sources. The CLKSRC(2..0) crosspoint switch
matrix defines which source is attached to each individual clock
output. CLKSRC(2..0) is set in Registers 44H, 45H, and 46H.
The remainder of register 46H(5:0) must be written with the
values stated in the register table when writing register values
46H(7:6).
When DIV1N is divisible by four, then CLKSRC(0,1,0) is
guaranteed to be rising edge phase-aligned with
CLKSRC(0,0,1). When DIV1N is six, then CLKSRC(0,1,1) is
guaranteed to be rising edge phase-aligned with
CLKSRC(0,0,1).
When DIV2N is divisible by four, then CLKSRC(1,0,1) is
guaranteed to be rising edge phase-aligned with
CLKSRC(1,0,0). When DIV2N is divisible by eight, then
CLKSRC(1,1,0) is guaranteed to be rising edge phase-aligned
with CLKSRC(1,0,0).
CLKOE – Clock Output Enable Control [09H(5..0)]
Each clock output has its own output enable, controlled by
register 09H(5..0). To enable an output, set the corresponding
CLKOE bit to 1. CLKOE settings are in Table 13 on page 8.
The output swing of LCLK1 through LCLK4 is set by V_DDL. The
output swing of CLK5 and CLK6 is set by V_DD.
Test, Reserved, and Blank Registers
Writing to any of the following registers causes the part to exhibit
abnormal behavior, as follows.
[00H to 08H]
[0AH to 0BH]
[0DH to 11H]
[14H to 3FH]
[43H]
[48H to FFH]
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved
– Reserved.
Table 11. Clock Output Setting
CLKSRC2 CLKSRC1 CLKSRC0
Definition and Notes
0
0
0
Reference input.
0
0
1
DIV1CLK/DIV1N. DIV1N is defined by register [OCH]. Allowable values for DIV1N are 4
to 127. If Divider Bank 1 is not being used, set DIV1N to 8.
0
1
0
DIV1CLK/2. Fixed /2 divider option. If this option is used, DIV1N must be divisible by 4.
0
1
1
DIV1CLK/3. Fixed /3 divider option. If this option is used, set DIV1N to 6.
1
0
0
DIV2CLK/DIV2N. DIV2N is defined by Register [47H]. Allowable values for DIV2N are 4
to 127. If Divider Bank 2 is not being used, set DIV2N to 8.
1
0
1
DIV2CLK/2. Fixed /2 divider option. If this option is used, DIV2N must be divisible by 4.
1
1
0
DIV2CLK/4. Fixed /4 divider option. If this option is used, DIV2N must be divisible by 8.
1
1
1
Reserved – do not use.
Table 12. Clock Output Register Setting
Address
D7
D6
D5
D4
D3
D2
D1
D0
44H CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for CLKSRC1 for
LCLK1
LCLK1
LCLK1
LCLK2
LCLK2
LCLK2
LCLK3
LCLK3
45H CLKSRC0 for CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for CLKSRC1 for CLKSRC0 for CLKSRC2 for
LCLK3
LCLK4
LCLK4
LCLK4
CLK5
CLK5
CLK5
CLK6
46H CLKSRC1 for CLKSRC0 for
1
1
1
1
1
1
CLK6
CLK6
Table 13. CLKOE Bit Setting
Address
D7
D6
09H
0
0
D5
CLK6
D4
CLK5
D3
LCLK4
D2
LCLK3
D1
LCLK2
D0
LCLK1
Document #: 38-07104 Rev. *K
Page 8 of 18
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