CY14B256Q1 Datasheet, PDF (8/26 Pages) Cypress Semiconductor – 256-Kbit (32 K × 8) Serial (SPI) nvSRAM

CY14B256Q1
CY14B256Q2
CY14B256Q3
SPI Operating Features
Power-Up
Power-up is defined as the condition when the power supply is
turned on and V_CC crosses Vswitch voltage. During this time, the
CS must be allowed to follow the V_CC voltage. Therefore, CS
must be connected to V_CC through a suitable pull-up resistor. As
a built in safety feature, CS is both edge sensitive and level
sensitive. After power-up, the device is not selected until a falling
edge is detected on CS. This ensures that CS must have been
HIGH, before going LOW to start the first operation.
As described earlier, nvSRAM performs a Power-Up RECALL
operation after power-up and therefore, all memory accesses are
disabled for t_FA duration after power-up. The HSB pin can be
probed to check the Ready or Busy status of nvSRAM after
power-up.
Power On Reset
A power on reset (POR) circuit is included to prevent inadvertent
writes. At power-up, the device does not respond to any
instruction until the V_CC reaches the POR threshold voltage
(V_SWITCH). After V_CC transitions the POR threshold, the device
is internally reset and performs an Power-Up RECALL operation.
During Power-Up RECALL all device accesses are inhibited.
The device is in the following state after POR:
■ Deselected (after power-up, a falling edge is required on CS
before any instructions are started).
■ Standby power mode
■ Not in the HOLD condition
■ Status Register state:
❐ Write Enable (WEN) bit is reset to ‘0’.
❐ WPEN, BP1, BP0 unchanged from previous STORE
operation
❐ Don’t care bits 4-6 are reset to ‘0’.
The WPEN, BP1, and BP0 bits of the Status Register are
nonvolatile bits and remain unchanged from the previous
STORE operation.
Before selecting and issuing instructions to the memory, a valid
and stable V_CC voltage must be applied. This voltage must
remain valid until the end of the instruction transmission.
Power-Down
At power-down (continuous decay of V_CC), when V_CC drops from
the normal operating voltage and below the V_SWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress and the last data bit D0 has been
received when the power goes down, it is allowed t_DELAY time to
complete the write. After this, all memory accesses are inhibited
and a conditional AutoStore operation is performed (AutoStore is
not performed if no writes have happened since the last RECALL
cycle). This feature prevents inadvertent writes to nvSRAM from
happening during power-down.
However, to completely avoid the possibility of inadvertent writes
during power-down, ensure that the device is deselected and is
in standby power mode, and the CS follows the voltage applied
on V_CC.
Active Power and Standby Power Modes
When CS is LOW, the device is selected and is in the active
power mode. The device consumes I_CC current, as specified in
DC Electrical Characteristics on page 15. When CS is HIGH, the
device is deselected and the device goes into the standby power
mode if a STORE or RECALL cycle is not in progress. If a
STORE or RECALL cycle is in progress, the device goes into the
standby power mode after the STORE or RECALL cycle is
completed. In the standby power mode, the current drawn by the
device drops to I_SB.
SPI Functional Description
The CY14B256Q1/CY14B256Q2/CY14B256Q3 uses an 8-bit
instruction register. Instructions and their operation codes are
listed in Table 2. All instructions, addresses, and data are
transferred with the MSB first and start with a HIGH to LOW CS
transition. There are, in all, 10 SPI instructions that provide
access to most of the functions in nvSRAM. Further, the WP,
HOLD and HSB pins provide additional functionality driven
through hardware.
Table 2. Instruction Set
Instruction
Category
Status Register
control
instructions
SRAM
Read/Write
instructions
Special NV
instructions
Reserved
Instruction
Name
Opcode
Operation
WREN
0000 0110 Set write enable
latch
WRDI
0000 0100 Reset write
enable latch
RDSR
0000 0101 Read Status
Register
WRSR 0000 0001 Write Status
Register
READ
0000 0011 Read data from
memory array
WRITE 0000 0010 Write data to
memory array
STORE 0011 1100 Software STORE
RECALL 0110 0000 Software
RECALL
ASENB 0101 1001 AutoStore Enable
ASDISB 0001 1001 AutoStore Disable
- Reserved - 0001 1110
The SPI instructions are divided based on their functionality in
the following types:
❐ Status Register access: RDSR and WRSR instructions
❐ Write protection functions: WREN and WRDI instructions
along with WP pin and WEN, BP0, and BP1 bits
❐ SRAM memory access: READ and WRITE instructions
❐ nvSRAM special instructions: STORE, RECALL, ASENB,
and ASDISB
Document Number: 001-53882 Rev. *E
Page 8 of 26
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