MB91F465KA Datasheet, PDF(78/86 Page) Cypress Semiconductor – 32-bit RISC, load/store architecture, five-stage pipeline

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MB91F465KA Datasheet, PDF (78/86 Pages) Cypress Semiconductor – 32-bit RISC, load/store architecture, five-stage pipeline

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Figure 2. Internal clock mode (master mode)

SCKn

VOL

for ESCR:SCES = 0

SCKn

for ESCR:SCES = 1

VOH

tSLOVI

SOTn

SINn

tSCYCI

VOH

VOL

tOVSHI

VOH

VOL

tIVSHI

VIH

VIL

MB91460K Series

VOL

VOH

tSHIXI

VIH

VIL

Figure 3. External clock mode (slave mode)

SCKn

for ESCR:SCES = 0

SCKn

for ESCR:SCES = 1

SOTn

SINn

VOH

VOL

tSLSHE

VOL

VOH

tSHSLE

VOL

tFE

VOH

tSLOVE

VOH

tRE

VOL

VOH

VOL

tIVSHE

VIH

VIL

VOH

tSHIXE

VIH

VIL

Document Number: 002-04602 Rev. *A

Page 78 of 86

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