MB91570 Datasheet, PDF (78/163 Pages) Cypress Semiconductor – 32-bit RISC, load/store architecture, 5-stage pipeline

MB91570 Series
Address
000530_H
000534_H
000538_H
00053C_H
000540_H to
00054C_H
000550_H
+0
CCRTSELR
[R/W] B,H,W
0------0
―
―
―
―
EIRR0[R/W] B,H,W
XXXXXXXX
Address offset value / Register name
+1
+2
CCPMUCR0 [R/W]
―
B,H,W
0-----00
―
―
―
―
―
―
+3
CCPMUCR1
[R/W] B,H,W
0--00000
―
―
―
―
―
―
ENIR0[R/W] B,H,W
00000000
ELVR0[R/W] B,H,W
00000000 00000000
Block
Clock control 2
Reserved
External interrupt
(INT0 to INT7)
000554_H
EIRR1[R/W] B,H,W
XXXXXXXX
ENIR1[R/W] B,H,W
00000000
ELVR1[R/W] B,H,W
00000000 00000000
External interrupt
(INT8 to INT15)
000558_H
―
00055C_H
―
000560_H
―
000564_H
―
―
―
WTCRH [R/W] B
------00
WTBRH [R/W] B
--XXXXXX
―
―
WTDR[R/W] H
00000000 00000000
WTCRM [R/W] B,H
00000000
WTCRL [R/W] B,H
----00-0
WTBRM [R/W] B
XXXXXXXX
WTBRL [R/W] B
XXXXXXXX
Reserved
Real-time clock
000568_H
WTHR [R/W] B,H
---00000
WTMR [R/W] B,H
--000000
WTSR [R/W] B
--000000
―
CSVCR[R/W]B
00056C_H
―
-001110-
―
―
-001010-*³
000570_H to
00057C_H
―
―
―
―
000580_H
REGSEL [R/W] B,H,W
0110011-
―
―
―
Clock supervisor
Reserved
Regulator control
000584_H
LVD5R [R/W] B,H,W
-------1
LVD5F [R/W] B,H,W
0-100--1
LVD [R/W] B,H,W
01000--0
―
000588_H to
00058C_H
―
―
―
―
Low-voltage detection
Reserved
Document Number: 002-04725 Rev.*A
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