W185 Datasheet, PDF (7/8 Pages) Cypress Semiconductor – Six Output Peak Reducing EMI Solution

W185
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
V_DD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V_DD pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V_DD connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5 shows a recommended 2-layer board layout.
Reference Output
R
Logic Input
XTAL Connection or Reference Input
XTAL Connection or NC
R
Clock Output
R
Clock Output
Clock Output
R
C1
0.1 µF
1
24
2
23
3
22
4
21
5
20
6
7
8
9
19 ^NC
18
17
16
R
Clock Output
10
15
Clock Output
11
14
R
12
13
Clock Output
R
FB
3.3V or 5V System Supply
C5
10 µF Tantalum
C3
0.1 µF
C4
0.1 µF
C2
0.1 µF
Figure 4. Recommended Circuit Configuration
Xtal Connection or Reference Input
Xtal Connection or NC
G
Clock Output
G
G
R
C1
R
C2
C3
R
C4
R
G
C1....C4 = High frequency supply decoupling
capacitor (0.1-µF recommended).
C5 = Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
G
R = _{Match value to line impedance}
G
FB = _{Ferrite Bead}
G = Via To GND Plane
G
Power Supply Input
(3.3V or 5V)
G
FB
C5
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
W185
W185-5
Package
Name
H
Package Type
24-Pin SSOP (209-mil)
Document #: 38-00809-A
7