W183 Datasheet, PDF (7/9 Pages) Cypress Semiconductor – Full Feature Peak Reducing EMI Solution

W183
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V_DD pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V_DD connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5 shows a recommended a 2-layer board layout
Xtal Connection or Reference Input 1
14
2
13
Xtal Connection or NC
3
12
GND ₄
11
5
10
6
9
7
8
R1
Clock
Output
3.3V or 5V System Supply
FB
C1
0.1 µF
C3
0.1 µF
C2
10 µF Tantalum
Figure 4. Recommended Circuit Configuration
Xtal Connection or Reference Input
Xtal Connectionor NC
C1, C3 = High frequency supply decoupling
capacitor (0.1-µF recommended).
C2 = Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
R1 = Match value to line impedance
FB = Ferrite Bead
G = Via To GND Plane
G
C3
G
G
C1
G
Power Supply Input
(3.3V or 5V)
R1
G
FB
C2
Clock Output
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
Package
Name
W183
G
W183-5
Package Type
14-Pin Plastic SOIC (150-mil)
Document #: 38-07158 Rev. *A
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