PLDC20RA10 Datasheet, PDF (7/14 Pages) Cypress Semiconductor – Reprogrammable Asynchronous CMOS Logic Device

PLDC20RA10
Switching Characteristics Over the Operating Range^{[3, 7, 8]}
Commercial
Military
–15
–20
–20
–25
–35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t_PD
Input or Feedback to
Non-Registered Output
15
20
20
25
35 ns
t_EA
Input to Output Enable
t_ER
Input to Output
Disable
15
20
15
20
20
30
20
30
35 ns
35 ns
t_PZX
Pin 13 to Output
Enable
12
15
15
20
25 ns
t_PXZ
Pin 13 to Output
Disable
12
15
15
20
25 ns
t_CO
Clock to Output
15
20
20
25
35 ns
t_SU
Input or Feedback
7
10
10
15
20
ns
Set-Up Time
t_H
t_P
t_WH
t_WL
f_MAX
t_S
Hold Time
3
5
3
5
5
ns
Clock Period
22
30
30
40
55
ns
(t_SU + t_CO)
Clock Width HIGH^[5]
10
13
12
18
25
ns
Clock Width LOW^[5]
10
13
12
18
25
ns
Maximum Frequency
45.5
33.3
33.3
25.0
18.1
MHz
(1/t_P)^[5]
Input of Asynchronous
15
20
20
25
40 ns
Set to Registered Output
t_R
Input of Asynchronous
Reset to Registered
Output
15
20
20
25
40 ns
t_ARW
Asynchronous Reset
15
Width^[5]
20
20
25
25
ns
t_ASW
Asynchronous S-Width^[5] 15
20
20
25
25
ns
t_AR
Asynchronous Set/
10
12
12
15
20
ns
Reset Recovery Time
t_WP
Preload Pulse Width
15
15
15
15
15
ns
t_SUP
Preload Set-Up Time
15
15
15
15
15
ns
t_HP
Preload Hold Time
15
15
15
15
15
ns
Notes:
7. Part (a) of AC Test Loads was used for all parameters except t_EA, t_ER, t_PZX and t_PXZ, which use part (b).
8. The parameters t_ER and t_PXZ are measured as the delay from the input disable logic threshold transition to V_OH - 0.5 V for an enabled HIGH output or V_OL
+0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.
Document #: 38-03012 Rev. **
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