CYV15G0404DXB_07 Datasheet, PDF (7/44 Pages) Cypress Semiconductor – Independent Clock Quad HOTLink II™ Transceiver with Reclocker

CYV15G0404DXB
Pin Configuration (Bottom View)
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A
OUT
B2–
IN
B2–
OUT
B1–
IN
B1–
V_CC
OUT
A2–
IN _GND OUT
A2–
A1–
IN
A1–
OUT
D2–
IN _GND OUT
D2–
D1–
IN
D1–
V_CC
OUT
C2–
IN
C2–
OUT
C1–
IN
C1–
B
OUT
B2+
IN
B2+
OUT
B1+
IN
B1+
V_CC
OUT
A2+
IN _GND OUT
A2+
A1+
IN
A1+
OUT
D2+
IN _GND OUT
D2+
D1+
IN
D1+
V_CC
OUT
C2+
IN
2+
OUT IN
C1+ C1+
C
TDO
LP
END
TRST LDTD
EN
V_CC
SPD RCLK _GND
SELD ENB
DATA
[1]
DATA
[3]
DATA
[5]
DATA _GND ULCC ULCD
[7]
V_CC
IN
IN
SELB SELC
TMS
TDI
D
TMEN3 SCAN VCC
EN2
LP
ENA
V_CC
ULCB
LP
ENB
GND ^DATA
[0]
DATA DATA DATA _GND SPD ULCA
[2]
[4]
[6]
SELC
V_CC
IN
IN RESET TCLK
SELA SELD
E
V_CC V_CC V_CC V_CC
V_CC V_CC V_CC V_CC
F
RX
TX
RX RCLK
STB[0] CLKOB STB[1] ENA
G
RX SPD LP SPD
DB[1] SELA ENC SELB
H ^{GND GND GND GND}
RCLK TX
RX
Rx
END DC[0] DC[7] DC[6]
TX
TX WREN TX
DC[1] DC[4]
DC[7]
GND GND GND GND
J
RX
RX
RX
RX
DB[2] DB[5] DB[0] STB[2]
K
LFIB RX
RX
RX
DB[7] DB[4] DB[3]
L
TX
RX
RX
RX
DB[6] CLKB– CLKB+ DB[6]
M
TX
TX REF REF
CLKB ERRB CLKB– CLKB+
N ^{GND GND GND GND}
TX
TX
TX
TX
DC[3] DC[2] DC[5] CTC[1]
TX
TX REF RX
CLKC CTC[0] CLKC– DC[2]
TX LFIC REF RX
DC[6]
CLKC+ DC[3]
TX RCLK RX
RX
ERRC ENC DC[5] DC[4]
GND GND GND GND
P
TX
TX
TX
TX
DB[2] DB[3] DB[4] DB[5]
R
TX
TX
TX
TX
DB[7] CTB[1] DB[0] DB[1]
T
V_CC V_CC V_CC V_CC
RX
RX
RX
RX
STC[1] STC[0] DC[0] DC[1]
RX
RX
TX
RX
CLKC– CLKC+ CLKOC STC[2]
V_CC V_CC V_CC V_CC
U
RX
RX
TX
RX
STA[1] STA[2] CTB[0] DA[2]
V_CC
TX
TX
CTA[0] DA[4]
GND
TX REF ADDR
DA[1] CLKD– [0]
TXC
TA[1]
GND ^RX
RX
DD[1] DD[2]
V_CC
TX
TX
CTD[1] DD[2]
TX
DD[1]
TX
DD[0]
V
RX
RX
RX
STA[0] DA[0] DA[3]
RX
DA[7]
V_CC
TX
TX _GND TX REF ADDR RX _GND RX
RX
DA[7] DA[3]
CLKOA CLKD+ [2] STD[2]
STD[0] DD[3]
V_CC
RX
TX
TX
TX
DD[6] CTD[0] DD[4] DD[3]
W
RX
RX REF LFIA
DA[1] DA[4] CLKA+
V_CC
TX
TX _GND TX
RX ADDR ADDR _GND RX
RX
DA[6] DA[2]
ERRA CLKA+ [1]
[3]
STD[1] DD[4]
V_CC
RX
CLKD–
LFID
TX
TX
DD[7] DD[5]
Y
RX
RX REF TX
DA[5] DA[6] CLKA– ERRD
Note
1. NC=Do Not Connect
V_CC
TX
DA[5]
TX _GND RX
TX
DA[0]
CLKA– CLKA
NC^[1] TX _GND RX
RX
CLKOD
DD[0] DD[5]
V_CC
RX
RX
CLKD+ DD[7]
TX
CLKD
TX
DD[6]
Document #: 38-02097 Rev. *B
Page 7 of 44
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