CY7C68310_05 Datasheet, PDF (7/34 Pages) Cypress Semiconductor – ISD-300LP™ Low-Power USB 2.0 to ATA/ATAPI Bridge IC

This part is not recommended for new designs
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
Bridge for new designs
CY7C68310
4.3.9 GPIO Pins
The GPIO pins allow for a general purpose Input/Output
interface. Configuration bytes 0x0E and 0x0F contain the
settings for the GPIO pins. See section 6.3 for details of how
to use the vendor-specific commands to utilize the GPIO
functionality. The status of the GPIO pins is also returned by a
USB interrupt event. See section 4.3.6 for SYSIRQ details.
Alternatively, if the hs_indicator config bit is set (bit 4 of
EEPROM address 0x0F), the GPIO2_nHS pin will reflect the
operating speed of the device.
4.3.10 LOWPWR
LOWPWR is an output pin that, when in a high-Z state,
indicates that the CY7C68310 is in a suspend state. When
LOWPWR output is driven ‘0’, the CY7C68310 is active.
4.3.11 nRESET
Asserting nRESET for a minimum of 1 ms after power rails are
stable will reset the entire chip. An RC reset circuit should be
used that ensures that no spurious resets occur.
4.3.12 ATAPUEN
This output provides control for the required host pull-up
resistors on the ATA interface. ATAPUEN is driven ‘0’ when the
ATA bus is inactive. ATAPUEN is driven ‘1’ when ATA bus is
active. ATAPUEN is set to a high-Z state along with all other
ATA interface pins when ATAEN is deasserted.
4.3.13 nPWR500
nPWR500 is an external pin that, when asserted, indicates
VBUS current may be drawn up to the limit specified by the
bMaxPower field of the USB configuration descriptors.
nPWR500 will only be asserted if VBUSPWRD is also
asserted. If the CY7C68310 enters a low-power state,
nPWR500 is deasserted. When normal operation is resumed,
nPWR500 is restored accordingly. The nPWR500 pin should
never be used to control power sources for the CY7C68310.
4.3.14 SCL, SDA_nIMODE
If an external EEPROM device is used to store configuration
information, the clock and data pins for the I²C-compatible port
should be connected to the configuration EEPROM and to
VCC through 2.2-kΩ resistors as shown in Figure 8-1. If
configuration information is to be obtained from the attached
ATA/ATAPI device (IMODE), SCL should be left as a no-
connect and SDA_nIMODE should be tied to GND.
4.3.15 DISKRDY
This input pin indicates the attached device is powered and
ready to begin communication with the CY7C68310.
DISKRDY polarity can be set using EEPROM address 0x05,
bit 0. DISKRDY qualifies the start of the CY7C68310 initial-
ization sequence. A state change from ‘0’ to ‘1’ on DISKRDY
will cause the CY7C68310 to wait for 25 ms before asserting
nATARESET and re-initializing the device. The ATA interface
state machines remain inactive and all of the ATA interface
signals are driven logic '0' if DISKRDY is not asserted
(assuming ATAEN = '1'). DISKRDY is filtered for 25 ms on the
asserting edge and cleared asynchronously on the
deasserting edge.
4.3.16 VBUSPWRD
The VBUSPWRD input pin indicates whether the device will
report itself as bus-powered or self-powered. VBUSPWRD
also qualifies the use of nPWR500. Based upon the state of
this pin at start-up, the CY7C68310 will request the amount of
current specified in the bMaxPower field of the USB Configu-
ration Descriptor. If VBUSPWRD is asserted, the CY7C68310
will report that the device is bus-powered. If VBUSPWRD is
deasserted, the CY7C68310 will report that the device is self-
powered.
4.3.17 VBUSPWRVLD
VBUSPWRVLD (USB VBUS Power Valid) indicates that
VBUS power is present at the USB connector. VBUSPWRVLD
qualifies driving the system’s 1.5KΩ pull-up resistor on D+ (the
USB specification only allows the device to source power to
D+ when the host is powered). VBUSPWRVLD is conditioned
so that it is only detected after valid chip configuration bits
have been loaded.
5.0 Functional Overview
5.1 USB Signaling Speeds
The CY7C68310 operates at two of the three signal rates that
are defined in the Universal Serial Bus Specification Revision
2.0:
• Full-speed, with a signaling bit rate of 12 Mbits/sec.
• High-speed, with a signaling bit rate of 480 Mbits/sec.
5.2 ATA Interface
The ATA/ATAPI port on the CY7C68310 is compliant with the
Information Technology–AT Attachment with Packet
Interface–6 (ATA/ATAPI-6) Specification, T13/1410D Rev 2a.
The CY7C68310 supports both ATAPI packet commands as
well as ATA commands (by use of ATA Command Blocks), as
outlined in Sections 5.2.1 and 5.2.2. Refer to the USB Mass
Storage Class (MSC) Bulk Only Transport Specification for
information on Command Block formatting. Additionally, the
CY7C68310 translates ATAPI SFF-8070i commands to ATA
commands for seamless integration of ATA devices with
generic Mass Storage Class BOT drivers. The CY7C68310
also provides a vendor-specific “event notify” ATA command
to automatically communicate certain USB and system events
to the attached device.
5.2.1 ATA Command Block (ATACB)
The ATA Command Block (ATACB) functionality provides a
means of passing ATA commands and ATA register accesses
for execution. ATACB commands are transferred in the
Command Block Wrapper Command Block (CBWCB) portion
of the Command Block Wrapper (CBW). The ATACB is distin-
guished from other command blocks by the first two bytes of
the command block matching the wATACBSignature. Only
command blocks that have a valid wATACBSignature are
interpreted as ATA Command Blocks. All other fields of the
CBW and restrictions on the CBWCB remain as defined in the
USB Mass Storage Class Bulk-Only Transport Specification.
The ATACB must be 16 bytes in length. Table 5-1 defines the
fields of the ATACB.
Document 38-08030 Rev. *J
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