CY7C601XX_11 Datasheet, PDF (7/68 Pages) Cypress Semiconductor – enCoRe™ II Low-Voltage Microcontroller Master or slave operation

CY7C601xx, CY7C602xx
8. Register Summary
Table 8-1. enCoRe II LV Register Summary
The XIO bit in the CPU flags register must be set to access the extended register space for all registers above 0xFF.
Addr Name
7
6
5
4
3
2
1
0
R/W
00
P0DATA
01
P1DATA
02
P2DATA
03
P3DATA
04
P4DATA
05
P00CR
06
P01CR
07–09
0A–0B
P02CR–
P04CR
P05CR– P06CR
0C
P07CR
0D
P10CR
0E
P11CR
0F
P12CR
10
P13CR
11–13 P14CR– P16CR
14
P17CR
15
P2CR
16
P3CR
17
P4CR
20
FRTMRL
21
FRTMRH
22
TCAP0R
23
TCAP1R
24
TCAP0F
25
TCAP1F
26
PITMRL
27
PITMRH
28
PIRL
29
PIRH
2A
TMRCR
2B
TCAPINTE
2C
TCAPINTS
30
CPUCLKCR
31
TMRCLKCR
32
CLKIOCR
P0.7
P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1
P0.2/INT0
P0.1/ P0.0/CLKIN
CLKOUT
P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL
P1.2
P1.1
P1.0
P2.7–P2.2
P2.1–P2.0
P3.7–P3.2
P3.1–P3.0
Reserved
P4.3–P4.0
Reserved Int enable Int act low TTL thresh High sink Open drain
Pull-up
enable
Output
enable
CLK output Int enable Int act low TTL thresh High sink Open drain
Pull-up
enable
Output
enable
Reserved
Int act low TTL thresh Reserved Open drain
Pull-up
enable
Output
enable
TIO output Int enable Int act low TTL thresh Reserved Open drain
Pull-up
enable
Output
enable
Reserved Int enable Int act low TTL thresh Reserved Open drain
Pull-up
enable
Output
enable
Reserved Int enable Int act low
Reserved
Output
enable
Reserved Int enable Int act low
Reserved
Open drain Reserved
Output
enable
CLK output Int enable Int act low TTL threshold Reserved Open drain
Pull-up
enable
Output
enable
Reserved Int enable Int act low Reserved High sink Open drain
Pull-up
enable
Output
enable
SPI use Int enable Int act low Reserved High sink Open drain
Pull-up
enable
Output
enable
Reserved Int enable Int act low Reserved High sink Open drain
Pull-up
enable
Output
enable
Reserved Int enable Int act low TTL thresh High sink Open drain
Pull-up
enable
Output
enable
Reserved Int enable Int act low TTL thresh High sink Open drain
Pull-up
enable
Output
enable
Reserved Int enable Int act low TTL thresh Reserved Open drain
Pull-up
enable
Output
enable
Free-running timer [7:0]
Free-running timer [15:8]
Capture 0 rising [7:0]
Capture 1 rising [7:0]
Capture 0 falling [7:0]
Capture 1 falling [7:0]
Prog interval timer [7:0]
Reserved
Prog interval timer [11:8]
Prog interval [7:0]
Reserved
Prog interval [11:8]
First edge
hold
8-bit capture prescale
Cap0 16-bit
enable
Reserved
Reserved
Cap1 fall
active
Cap1 rise
active
Cap0 fall
active
Cap0 rise
active
Reserved
Cap1 fall
active
Cap1 rise
active
Cap0 fall
active
Cap0 rise
active
Reserved
CPU
CLK select
TCAPCLK divider
TCAPCLK select
ITMRCLK divider
ITMRCLK select
Reserved
XOSC
Select
XOSC
Enable
EFTB
Disabled
CLKOUT select
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
----bbbb
-bbbbbbb
bbbbbbbb
--bb-bbb
bbbb-bbb
-bbb-bbb
-bb----b
-bb--b-b
bbbb-bbb
-bb-bbbb
bbb-bbbb
-bb-bbbb
-bbbbbbb
-bbbbbbb
-bbb-bbb
bbbbbbbb
bbbbbbbb
rrrrrrrr
rrrrrrrr
rrrrrrrr
rrrrrrrr
rrrrrrrr
----rrrr
bbbbbbbb
----bbbb
bbbbb---
----bbbb
----bbbb
-------b
bbbbbbbb
---bbbbb
Default
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
10001111
00000000
Document 38-16016 Rev. *J
Page 7 of 68