CY7C1511JV18 Datasheet, PDF (7/29 Pages) Cypress Semiconductor – 72-Mbit QDR-II SRAM 4-Word Burst Architecture

CY7C1511JV18, CY7C1526JV18
CY7C1513JV18, CY7C1515JV18
Pin Definitions (continued)
Pin Name
IO
Pin Description
CQ
Echo Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the Switching Characteristics on page 24.
CQ
Echo Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the Switching Characteristics on page 24.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q_[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to V_DDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The
timings in the DLL turned off operation differs from those listed in this data sheet. For normal operation,
this pin is connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR-I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with QDR-I timing.
TDO
Output TDO for JTAG.
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
V_REF
Input- Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
Reference measurement points.
V_DD
V_SS
V_DDQ
Power Supply Power Supply Inputs to the Core of the Device.
Ground Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Document Number: 001-12560 Rev. *E
Page 7 of 29
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