CY7C1372BV25 Datasheet, PDF (7/26 Pages) Cypress Semiconductor – 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture

CY7C1372BV25
CY7C1370BV25
(BWS) input will selectively write to only the desired bytes.
Bytes not selected during a byte Write operation will remain
unaltered. A Synchronous self-timed Write mechanism has
been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple byte Write operations.
Because the CY7C1370BV25/72BV25 is a common I/O
device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ and DP
(DQ_a,b,c,d/DP_a,b,c,d for CY7C1370BV25 and DQ_a,b/DP_a,b for
CY7C1372BV25) inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ and DP (DQ_a,b,c,d/DP_a,b,c,d
for CY7C1370BV25 and DQ_a,b/DP_a,b for CY7C1372BV25)
Cycle Description Truth Table^{[1, 2, 3, 4, 5, 6]}
are automatically three-stated during the data portion of a
Write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1370BV25/72BV25 has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subse-
quent clock rise, the chip enables (CE₁, CE₂, and CE₃) and
WE inputs are ignored and the burst counter is incremented.
The correct BWS (BWS_a,b,c,d for CY7C1370BV25 and BWS_a,b
for CY7C1372BV25) inputs must be driven in each cycle of the
burst Write in order to Write the correct bytes of data.
Operation
Deselected
Address
Used
External
Suspend
–
Begin Read
Begin Write
External
External
Burst Read
Operation
Internal
Burst Write
Operation
Internal
ADV/L
CE CEN D/
WE BWS_x CLK
Comments
1
0
L
X
X L-H
I/Os three-state following next
recognized clock.
X
1
X
X
X L-H
Clock ignored, all operations
suspended.
0
0
0
1
X L-H
Address latched.
0
0
0
0
Valid L-H
Address latched, data presented
two valid clocks later.
X
0
1
X
X L-H
Burst Read operation. Previous
access was a Read operation.
Addresses incremented internally in
conjunction with the state of Mode.
X
0
1
X
Valid L-H
Burst Write operation. Previous
access was a Write operation.
Addresses incremented internally in
conjunction with the state of MODE.
Bytes written are determined by
BWS_[d:a].
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
A[1:0]
A[1:0]
A[1:0]
00
01
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A[1:0]
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
A[1:0]
A[1:0]
A[1:0]
00
01
10
01
10
11
10
11
00
11
00
01
Fourth
Address
A[1:0]
11
00
01
10
Notes:
1. X = ”Don't Care,” 1 = Logic HIGH, 0 = Logic LOW, CE stands for ALL Chip Enables active. BWS_x = 0 signifies at least one Byte Write Select is active, BWS_x= Valid
signifies that the desired Byte Write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWSx. See Write Cycle Description table for details.
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN = 1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
Document #: 38-05252 Rev. **
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