CY7C1266KV18 Datasheet, PDF (7/28 Pages) Cypress Semiconductor – 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1266KV18, CY7C1277KV18
CY7C1268KV18, CY7C1270KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ_[x:0]
LD
Input output-
synchronous
Input-
synchronous
Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the K and K clocks during read operations. When read access is deselected,
Q_[x:0] are automatically tristated.
CY7C1266KV18  DQ_[7:0]
CY7C1277KV18  DQ_[8:0]
CY7C1268KV18  DQ_[17:0]
CY7C1270KV18  DQ_[35:0]
Synchronous load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
NWS₀,
NWS₁
Input-
synchronous
Nibble write select 0, 1  active LOW (CY7C1266KV18 only). Sampled on the rising edge of the K and
K clocks during write operations. Used to select which nibble is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered.
NWS₀ controls D_[3:0] and NWS₁ controls D_[7:4].
All the nibble write selects are sampled on the same edge as the data. Deselecting a nibble write select
ignores the corresponding nibble of data and it is not written into the device.
BWS₀,
BWS₁,
BWS₂,
BWS₃
Input-
synchronous
Byte write select 0, 1, 2, and 3  active LOW. Sampled on the rising edge of the K and K clocks during
write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1277KV18  BWS₀ controls D_[8:0]
CY7C1268KV18 BWS₀ controls D_[8:0] and BWS₁ controls D_[17:9].
CY7C1270KV18 BWS₀ controls D_[8:0], BWS₁ controls D_[17:9], BWS₂ controls D_[26:18] and BWS₃ controls
D_[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
A
Input- Address inputs. Sampled on the rising edge of the K clock during active read and write operations. These
synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
4 M × 8 (2 arrays each of 2 M × 8) for CY7C1266KV18 and 4 M × 9 (2 arrays each of 2 M ×9) for
CY7C1277KV18, 2 M × 18 (2 arrays each of 1 M × 18) for CY7C1268KV18, and 1 M × 36 (2 arrays each
of 512 K × 36) for CY7C1270KV18.
R/W
Input- Synchronous read or write input. When LD is LOW, this input designates the access type (read when
synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
QVLD
Valid output Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
K
Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q_[x:0]. All accesses are initiated on the rising edge of K.
K
Input clock Negative input clock input. K is used to capture synchronous data being presented to the device and
to drive out data through Q_[x:0].
CQ
Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24.
CQ
Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24.
ZQ
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q_[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to V_DDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Document Number: 001-57835 Rev. *C
Page 7 of 28
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