CY7C106D Datasheet, PDF (7/11 Pages) Cypress Semiconductor – 1-Mbit (256K x 4) Static RAM

CY7C106D
CY7C1006D
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled) ^{[18, 19]}
ADDRESS
CE
t_SA
WE
DATA IO
t_WC
t_SCE
t_AW
t_PWE
t_SD
DATA VALID
t_HA
t_HD
Write Cycle No. 2 (WE Controlled, OE HIGH During Write) ^{[18, 19]}
t_WC
ADDRESS
t_SCE
CE
t_AW
t_SA
t_PWE
WE
OE
DATA IO
t_HZOE
t_SD
DATA VALID
t_HA
t_HD
Notes
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
19. Data IO is high impedance if OE = V_IH.
Document #: 38-05459 Rev. *E
Page 7 of 11
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