CY7B9930V_07 Datasheet, PDF (7/11 Pages) Cypress Semiconductor – High Speed Multifrequency PLL Clock Buffer

RoboClockII™ Junior,
CY7B9930V, CY7B9940V
Switching Characteristics
Over the Operating Range^{[7, 8, 9, 10, 11]} (continued)
Parameter
Description
t_LOCK
t_RELOCK1
t_RELOCK2
t_ODCV
t_PWH
t_PWL
t_PDEV
t_OAZ
t_OZA
PLL lock time from power up
PLL relock time (from same frequency, different phase) with
stable power supply
PLL Relock Time (from different frequency, different phase) with
Stable Power Supply^[17]
Output duty cycle deviation from 50%^[11]
Output HIGH time deviation from 50%^[18]
Output LOW time deviation from 50%^[18]
Period deviation when changing from reference to reference^[19]
DIS[1:2] HIGH to output high impedance from ACTIVE^{[12, 20]}
DIS[1:2] LOW to output ACTIVE from output is high
impedance^{[20, 21]}
CY7B9930/40V-2
Min. Max.
–
10
–
500
CY7B9930/40V-5
Min. Max.
–
10
–
500
–
1000
–
1000
–1.0
1.0
–1.0
1.0
–
1.5
–
1.5
–
2.0
–
2.0
–
0.025
–
0.025
1.0
10
1.0
10
0.5
14
0.5
14
AC Test Loads and Waveform
See note. [22]
3.3V
R1
For LOCK output only For all other outputs
OUTPUT
R1 = 910Ω
R2 = 910Ω
R1 = 100Ω
R2 = 100Ω
C_L
C_L < 30 pF
C_L < 25 pF up to 185 MHz
R2
(Includes fixture and ^{10 pF from 185 to 200 MHz}
probe capacitance)
(a) LVTTL AC Test Load
Unit
ms
μs
μs
ns
ns
ns
UI
ns
ns
3.3V
GND
< 1 ns
2.0V
0.8V
2.0V
0.8V
< 1 ns
(b) TTL Input Test Waveform
Notes
17. f_NOM must be within the frequency range defined by the same FS state.
18. t_PWH is measured at 2.0V. t_PWL is measured at 0.8V.
19. UI = Unit Interval. Examples: 1 UI is a full period. 0.1 UI is 10% of period.
20. Measured at 0.5V deviation from starting voltage.
21. For t_OZA minimum, C_L = 0 pF. For t_OZA maximum, C_L= 25 pF to 18 MHz, 10 pF from 185 to 200 MHz.
22. These figures are for illustration only. The actual ATE loads may vary.
Document Number: 38-07271 Rev. *C
Page 7 of 11
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