CY62128EV30_1106 Datasheet, PDF (7/18 Pages) Cypress Semiconductor – 1-Mbit (128 K x 8) Static RAM Automatic power-down when deselected

Switching Characteristics
Over the Operating Range
Parameter ^{[14, 15]}
Description
Read Cycle
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
Write Cycle ^[18]
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_SD
t_HD
t_HZWE
t_LZWE
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z ^[16]
OE HIGH to high Z ^{[16, 17]}
CE LOW to low Z ^[16]
CE HIGH to high Z ^{[16, 17]}
CE LOW to power-up
CE HIGH to power-down
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE LOW to high Z ^{[16, 17]}
WE HIGH to low Z ^[16]
CY62128EV30 MoBL^®
45 ns (Industrial)
Unit
Min
Max
45
–
ns
–
45
ns
10
–
ns
–
45
ns
–
22
ns
5
–
ns
–
18
ns
10
–
ns
–
18
ns
0
–
ns
–
45
ns
45
–
ns
35
–
ns
35
–
ns
0
–
ns
0
–
ns
35
–
ns
25
–
ns
0
–
ns
–
18
ns
10
–
ns
Notes
14. CE is the logical combination of CE₁ and CE₂. When CE₁ is LOW and CE₂ is HIGH, CE is LOW; when CE₁ is HIGH or CE₂ is LOW, CE is HIGH.
15.
Test Conditions for
pulse levels of 0 to
all parameters other than tri-state parameters assume
V_CC(typ), and output loading of the specified I_OL/I_OH as
signal transition time of 3 ns
shown in the AC Test Loads
or less (1 V/ns),
and Waveforms
timing reference
on page 5.
levels
of
V_CC(typ)/2,
input
16. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
17. t_HZOE, t_HZCE, and t_HZWE transitions are measured when the output enter a high impedance state.
18.
The internal write time of the
a write by going INACTIVE.
memory
The data
is defined by the
input setup and
overlap of WE, CE
hold timing should
b=eVr^Ie^L.feArlel nscigendatlso
must be ACTIVE to initiate
the edge of the signal that
a write and
terminates
any
the
of these
write.
signals
can
terminate
Document #: 38-05579 Rev. *J
Page 7 of 18
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